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WCET analysis of instruction caches with prefetching

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Published:13 June 2007Publication History

ABSTRACT

Instruction prefetching is an effective technique to reduce the instruction cache miss latency for improving the average-case performance. For real-time systems, however, the use of instruction prefetching will only besuitable if a reasonably tight worst-case performance of programs using instruction prefetching can be predicted. This paper presents an approach to modeling and computing the worst-case instruction cache performance with prefetching. Our experimental results indicate that instruction prefetching can benefit both the average-case and worst-case performance; however, the degree of the worst-case performance improvement due to instruction prefetching is less than that of the average-case performance, thus leading to increased time variation for real-time computing. Also, we find that the prefetching distance can significantly impact the worst-case performance analysis with instruction prefetching. Particularly, when the prefetching distance is equal to the L1 miss penalty, the worst-case execution time with instruction prefetching is minimized (i.e., optimal).

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        • Published in

          cover image ACM Conferences
          LCTES '07: Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
          June 2007
          258 pages
          ISBN:9781595936325
          DOI:10.1145/1254766
          • cover image ACM SIGPLAN Notices
            ACM SIGPLAN Notices  Volume 42, Issue 7
            Proceedings of the 2007 LCTES conference
            July 2007
            241 pages
            ISSN:0362-1340
            EISSN:1558-1160
            DOI:10.1145/1273444
            Issue’s Table of Contents

          Copyright © 2007 ACM

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          Association for Computing Machinery

          New York, NY, United States

          Publication History

          • Published: 13 June 2007

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