Abstract
Embedded systems serve an emerging and diverse set of applications. As a result, more computational and storage capabilities are added to accommodate ever more demanding applications. Unfortunately, adding more resources typically comes on the expense of higher energy costs. New chip design with Multiple Clock Domains (MCD) opens the opportunity for fine-grain power management within theprocessor chip. When used with dynamic voltage scaling (DVS), we can control the voltage and power of each domain independently. A significant power and energy improvement has been shown when using MCD design in comparison to managing a single voltage domain for the whole chip, as in traditional chips with global DVS.
In this paper, we propose PACSL a Power-Aware Compiler-based approach using Supervised Learning. PACSL automatically derives an integrated CPU-core and on-chip L2 cache DVS policy tailored to a specific system and workload. Our approach uses supervised machine learning to discover a policy, which relies on monitoring a few performance counters. We present our approach detailing the role of a compiler in constructing a custom power management policy. We also discuss some implementation issues associated with our technique. We show that PACSL improves on traditional power management techniques that are used in general MCD chips. Our technique saves 22% on average (up to 46%) in energy-delay product over a DVS technique that applies independent DVS decisions in each domain. Compared to no-power management, our technique improves energy-delay product by 26% on average (up to 64%).
- T. D. Burd and R. W. Brodersen. Energy efficient CMOS microprocessor design. In Proc. of The HICSS Conference, Jan. 1995. Google Scholar
Digital Library
- J. Cavazos, J. Eliot, and B. Moss. Inducing heuristics to decide whether to schedule. In PLDI '04: Proceedings of the ACM SIGPLAN 2004 conference on Programming language design and implementation, pages 183--194. ACM Press, 2004. Google Scholar
Digital Library
- W. W. Cohen. Fast effective rule induction. In Proceedings of the 12th International Conference on Machine Learning, June 1995.Google Scholar
Cross Ref
- X. Fan, C. S. Ellis, and A. R. Lebeck. The synergy between power-aware memory systems and processor voltage scaling. In Proceedings of the Workshop on Power-Aware Computer Systems (PACS'03), 2003. Google Scholar
Digital Library
- J. Furnkranz and G. Widmer. Incremental reduced error pruning. In International Conference on Machine Learning, pages 70--77, 1994.Google Scholar
Cross Ref
- G. Magklis, M. L. Scott, G. Semeraro, D. H. Albonesi, and S. Dropsho. Profile-based dynamic voltage and frequency scaling for a multiple clock domain microprocessor. In Proceedings of the 30th International Symposium on Computer Architecture (ISCA'03), June 2003. Google Scholar
Digital Library
- G. Magklis, G. Semeraro, D. H. Albonesi, S. G. Dropsho, S. Dwarkadas, and M. L. Scott. Dynamic frequency and voltage scaling for a multiple clock domain microprocessor. IEEE Micro, 23(6):62--68, 2003. Google Scholar
Digital Library
- A. Miyoshi, C. Lefurgy, E. Hensbergen, R. Rajamony, and R. Rajkumar. Critical power slope: Understanding the runtime effects of frequency scaling. In Proceedings of the 16th Annual ACM International Conference on Supercomputing, New York, June 2002. Google Scholar
Digital Library
- T. Pering, T. Burd, and R. Brodersen. Voltage scheduling in the lparm microprocessor system. In Proc. of the International Symposium on Low Power Electronics and Design (ISLPED'00), pages 96--101, 2000. Google Scholar
Digital Library
- J. Pouwelse, K. Langendoen, and H. Sips. Application-directed voltage scaling. In IEEE Transactions on Very Large Scale Integration (TVLSI), Sept. 2002. Google Scholar
Digital Library
- K. Puttaswamy, K. Choi, J. Park, V. J. M. III, A. Chatterjee, and P. Ellervee. System level power-performance trade-offs in embedded systems using voltage and frequency scaling of off-chip buses and memory. In Proceedings of International Symposium on System Synthesis (ISSS'02), Kyoto, Japan, 2002. Google Scholar
Digital Library
- C. Rusu, N. AbouGhazaleh, A. Ferreria, R. Xu, B. Childers, R. Melhem, and D. Mossé. Integrated cpu and l2 cache frequency/voltage scaling using supervised learning. In Workshop on Statistical and Machine learning approaches applied to ARchitectures and compilation (SMART), 2007.Google Scholar
- T. Sherwood, E. Perelman, G. Hamerly, and B. Calder. Automatically characterizing large scale program behavior. In Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems, 2002. Google Scholar
Digital Library
- T. Sherwood, S. Sair, and B. Calder. Phase tracking and prediction. In Proceedings of the 30th International Symposium on Computer Architecture (ISCA'03), 2003. Google Scholar
Digital Library
- M. Weiser, B. Welch, A. Demers, and S. Shenker. Scheduling for reduced cpu energy. In First Symposium on Operating Systems Design and Implementation, pages 13--23, 1994. Google Scholar
Digital Library
- J. Wildstrom, E. Witchel, and R. J. Mooney. Towards self-configuring hardware for distributed computer systems. In ICAC '05: Proceedings of the Second International Conference on Automatic Computing, pages 241--249, Washington, DC, USA, 2005. IEEE Computer Society. Google Scholar
Digital Library
- I. H. Witten and E. Frank. Data Mining: Practical machine learning tools and techniques. Morgan Kaufmann, San Francisco, 2005. Google Scholar
Digital Library
- Q. Wu, P. Juang, M. Martonosi, and D. W. Clark. Formal online methods for voltage/frequency control in multiple clock domain microprocessors. In ASPLOS-XI: Proc Intl Conf on Architectural support for programming languages and operating systems, pages 248--259, 2004. Google Scholar
Digital Library
- Y. Zhu, D. H. Albonesi, and A. Buyuktosunoglu. A high performance, energy efficient gals processor microarchitecture with reduced implementation complexity. In ISPASS'05: Proc Intl Symp on Performance Analysis of Systems and Software, pages 42--53, 2005. Google Scholar
Digital Library
Index Terms
Integrated CPU and l2 cache voltage scaling using machine learning
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Integrated CPU and l2 cache voltage scaling using machine learning
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