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Integrated CPU and l2 cache voltage scaling using machine learning

Published:13 June 2007Publication History
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Abstract

Embedded systems serve an emerging and diverse set of applications. As a result, more computational and storage capabilities are added to accommodate ever more demanding applications. Unfortunately, adding more resources typically comes on the expense of higher energy costs. New chip design with Multiple Clock Domains (MCD) opens the opportunity for fine-grain power management within theprocessor chip. When used with dynamic voltage scaling (DVS), we can control the voltage and power of each domain independently. A significant power and energy improvement has been shown when using MCD design in comparison to managing a single voltage domain for the whole chip, as in traditional chips with global DVS.

In this paper, we propose PACSL a Power-Aware Compiler-based approach using Supervised Learning. PACSL automatically derives an integrated CPU-core and on-chip L2 cache DVS policy tailored to a specific system and workload. Our approach uses supervised machine learning to discover a policy, which relies on monitoring a few performance counters. We present our approach detailing the role of a compiler in constructing a custom power management policy. We also discuss some implementation issues associated with our technique. We show that PACSL improves on traditional power management techniques that are used in general MCD chips. Our technique saves 22% on average (up to 46%) in energy-delay product over a DVS technique that applies independent DVS decisions in each domain. Compared to no-power management, our technique improves energy-delay product by 26% on average (up to 64%).

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      • Published in

        cover image ACM SIGPLAN Notices
        ACM SIGPLAN Notices  Volume 42, Issue 7
        Proceedings of the 2007 LCTES conference
        July 2007
        241 pages
        ISSN:0362-1340
        EISSN:1558-1160
        DOI:10.1145/1273444
        Issue’s Table of Contents
        • cover image ACM Conferences
          LCTES '07: Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
          June 2007
          258 pages
          ISBN:9781595936325
          DOI:10.1145/1254766

        Copyright © 2007 ACM

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        Association for Computing Machinery

        New York, NY, United States

        Publication History

        • Published: 13 June 2007

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