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Optimistic coalescing for heterogeneous register architectures

Published:13 June 2007Publication History
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Abstract

In this paper, Optimistic coalescing has been proven as an elegant and effective technique that provides better chances of safely coloring more registers in register allocation than other coalescing techniques. Its algorithm originally assumes homogeneous registers which are all gathered in the same register file. Although this register architecture is still common in most general-purpose processors, embedded processors often contain heterogeneous registers which are scattered in physically different register files dedicated for each dissimilar purpose and use. In this work, we developed a modified algorithm for optimal coalescing that helps a register allocator for an embedded processor to better handle such heterogeneity of the register architecture. In the experiment, an existing register allocator was able to achieve up to 10% reduction in code size through our coalescing, and avoid many spills that would have been generated without our scheme.

References

  1. Gregory J. Chaitin, Register allocation and spilling via graph coloring, SIGPLAN Symposium on Compiler Construction, 1982 Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. V. Zivojnovic, et al., DSP processor/compiler co-design: a quantitative approach, 9th International Symposium on System Synthesis p. 108 Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. Jinpyo Park, Soo-Mook Moon, Optimistic Register Coalescing, in the Proceedings of Parallel Architectures and Compilation Techniques (PACT) 98, 1998 Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. T. Kong et. al, Precise register allocation for irregular architectures. In Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture (MICRO), page 297--307. IEEE computer Society Press, 1998. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. B.Scholz et. al., Register allocation for irregular architectures. In Proceedings of the joint conference on Languages, Compilers and Tools for Embedded Systems (LCTES), pages 139--148. ACM Press, 2002. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. D. Koes et. al., A Progressive Register Allocator for Irregular Architectures. In proceedings of the international Symposium on Code Generation and Optimization (CGO), 2005. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. Michael D. Smith, et. al., A Generalized Algorithm for Graph-coloring register allocation, in the Proceedings of the ACM SIGPLAN 2004 conference on Programming language design and implementation (PLDI) 04, Vol39, Issue 6, 2004 Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. Lal George, et. al., Iterated Register Coalescing, ACM Transactions on Programming Languages and Systems, Vol. 18, N0. 3, May 1996, Pages 300--324 Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. Minwook Ahn, et. al., A Code Generation Approach for Heterogeneous Register Architectures, in the Proceedings of the 11th Annual Workshop on the Interaction between Compilers and Computer Architecture, 2007Google ScholarGoogle Scholar
  10. C. Liem, T. et. al., Register Assignment through Resource Classification for ASIP Microcode Generation, in the Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, 1994 Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. P. Paulin, et. al., DSP Design Tool Requirements for Embedded Systems: A Telecommunications Industrial Perspective, in Journal of VLSI Signal Processing, 1994 Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. H. Feuerhahn, Data Flow Driven Resource Allocation in a Retargetable Microde Compiler, International Symposium on Microarchitecture, 1988, pp. 105--107 Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. R. Stallman, Using and Porting GNU CC, Free Software Foundation, June 1993Google ScholarGoogle Scholar
  14. Guido Araujo, et. al., Code Generation for Fixed-Point DSPs, ACM Transactions on Design Automation of Electronic Systems(TODAES), Vol 3, Issue 2, 1998 Google ScholarGoogle ScholarDigital LibraryDigital Library
  15. V. Zivojnovic, et. al., DSPstone: A DSP-Oriented Benchmarking Methodology, in the Proceedings of International Conference on Signal Processing Applications and Technology (ICSPAT)'94 -- Dallas, Oct. 1994.Google ScholarGoogle Scholar
  16. Chunho Lee, et. al., MediaBench: a tool for evaluating and synthesizing multimedia andcommunications systems, in the Proceedings of 30th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 1997. Google ScholarGoogle ScholarDigital LibraryDigital Library
  17. Jenq-Kuen Lee, et. al., Copy Propagation Optimizations for VLIW DSP Processors with Distributed Register Files, in the Proceedings of the 19th International Workshop on Languages and Compilers for Parallel Computing (LCPC) 2006Google ScholarGoogle Scholar
  18. Jean-Marc Daveau, et. al., A retargetable register allocation framework for embedded processors, in the Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), 2004 Google ScholarGoogle ScholarDigital LibraryDigital Library
  19. P. Briggs. Register Allocation via Graph Coloring, Ph.d Thesis, Rice University, April 1992 Google ScholarGoogle ScholarDigital LibraryDigital Library

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