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Enabling compiler flow for embedded VLIW DSP processors with distributed register files

Published:13 June 2007Publication History
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Abstract

High-performance and low-power VLIW DSP processors are increasingly deployed on embedded devices to process video and multimedia applications. For reducing power and cost in designs of VLIW DSP processors, distributed register files and multi-bank register architectures are being adopted to eliminate the amount of read/write ports in register files. This presents new challenges for devising compiler optimization schemes for such architectures. In this paper, we address the compiler optimization issues for PAC architecture, which is a 5-way issue DSP processor with distributed register files. We present an integrated flow to address several phases of compiler optimizations in interacting with distributed register files and multi-bank register files in the layer of instruction scheduling, software pipelining, and data flow optimizations. Our experiments on a novel 32-bit embedded VLIW DSP (known as the PAC DSP core) exhibit the state of the art performance for embedded VLIW DSP processors with distributed register files by incorporating our proposed schemes in compilers.

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    • Published in

      cover image ACM SIGPLAN Notices
      ACM SIGPLAN Notices  Volume 42, Issue 7
      Proceedings of the 2007 LCTES conference
      July 2007
      241 pages
      ISSN:0362-1340
      EISSN:1558-1160
      DOI:10.1145/1273444
      Issue’s Table of Contents
      • cover image ACM Conferences
        LCTES '07: Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
        June 2007
        258 pages
        ISBN:9781595936325
        DOI:10.1145/1254766

      Copyright © 2007 ACM

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      Association for Computing Machinery

      New York, NY, United States

      Publication History

      • Published: 13 June 2007

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