David A. Poplawski
ABSTRACT
JLS is a GUI-based digital logic simulation tool specifically designed for use in a wide range of digital logic and computer organization courses. It is comparable in features and functionality to commercial products, but includes many student and instructor-friendly aspects not found in those products such as state-machine and truth table editors, extensive error checking, and multiple simulation-result views. Students quickly become proficient in its use, enabling them to concentrate on circuit design and debugging issues. The circuit drawing interface is convenient enough to allow instructors to use it for classroom presentations, and circuits can be modified and tested so quickly that it promotes exploring alternatives not prepared for in advance. Its non-interractive (batch) execution capability, with parameter settings, configuration files and textual output simplifies the grading of large numbers of student projects.
- C. Burch. Logisim: a graphical system for logic circuit design and simulation. J. Educ. Resour. Comput., 2(1):5--16, 2002. Google Scholar
Digital Library
- Capilano Computing. LogicWorks 5 Interractive Software. Prentice Hall, 2003.Google Scholar
- J. Hansen, 2006. http://www.tkgate.org.Google Scholar
- D. Patterson and J. Hennessy. Computer Organization and Deisgn: The Hardware/Software Interface. Morgan Kaufmann, third edition, 2005. Google ScholarDigital Library
- A. Tetzl, 2006. http://www.tetzl.de/java_logic_simulator.html.Google Scholar
- G. S. Wolffe, W. Yurcik, H. Osborne, and M. A. Holliday. Teaching computer organization/architecture with limited resources using simulators. In SIGCSE '02: Proceedings of the 33rd SIGCSE technical symposium on Computer science education, pages 176--180, New York, NY, USA, 2002. ACM Press. Google ScholarDigital Library
Index Terms
A pedagogically targeted logic design and simulation tool
Recommendations
A Mathematical Model Characterizing Four-Phase MOS Circuits for Logic Simulation
Abstract Four-phase MOS circuits exhibit many peculiar features not observed in other families of logic circuits. In this paper, a mathematical model which characterizes the circuits is presented for logic simulation. It is shown that this model enables ...
Levelized compiled code multi-delay logic simulation
Levelized Compiled Code (LCC) multi-delay simulation is an idea whose time has come. Although it is not a new idea, when it was first proposed the hardware and software technology of the time was not capable of meeting the demands of such a simulation ...
Time-parallel multi-delay logic simulation
Multi-delay logic simulation may perform many logic simulations for each gate in the circuit during the simulation of a single input vector. Conventional event driven simulation will perform each of these gate-simulations as a separate operation, ...
Comments