
References
- 1.T. Amon and G. Borriello. On the Specification of Timing Behavior. In TAU 1990 A CM Int. Workshop on Tzming Issues, Vancouver, Canada, August 1990.Google Scholar
- 2.G. Borriello and R. Katz. Design Frames: A New System Integration Methodology. In Chapel Hill [email protected] ence on VLS{, May 1985.Google Scholar
- 3.M. Browne, E. Clarke, and D. Dill. Automatic Circuit Verification Using Temporal Logic: Two New Examples. In Formal Aspects of VLSI Design. Elsevier Science, 1986.Google Scholar
- 4.R. E. Bryant. Can a Simulator Verify a Circuit. In G. J. Milne and P. A. Subramanyan, editors, Formal Aspects of VLSI Design. Elsevier Science, 1986.Google Scholar
- 5.D. Doukas. A New Specification Model for Timing Constraznts and Ejficzent Methods for their Verification. PhD thesis, Princeton University, January 1991. CS- TR-297-90. Google Scholar
Digital Library
- 6.G. Gibson, D. Wood, and S. Eggers. SPUR Project Technical Documentation. UC Berkeley, 1986.Google Scholar
- 7.M. Gordon. HOL: A Proof Generating System for Higher-Order Logic. In VLSISpecification, Verzficat~on and Synthesis. Kluwer Academic, 1988.Google Scholar
- 8.R. B. Hitchcock. Timing Verification and the Timing Analysis Program. In 19th DA C, 1982. Google Scholar
Digital Library
- 9.Intel Corporation. Intel Multibus Specification, 1982.Google Scholar
- 10.A. Kara, R. Rastogi, and K. Kawamura. An Expert System to Automate Timing Design. IEEE Design Test of Computers, October 1988. Google Scholar
Digital Library
- 11.A. Martello, S. Levitan, and D. Chiarulli. Timing Verification Using HDTV. In 27th DAC, 1990. Google Scholar
Digital Library
- 12.M. C. McFarland. CPA: Giving an Account of Timed System Behavior. In TA U 1990 A CM Int. Workshop on Timing Issues, Vancouver, Canada, August 1990.Google Scholar
- 13.T. McWilliams. Verification of Timing Constraints on Large Digital Systems. PhD thesis, Lawrence Livermore Laboratory, May 1980. Google Scholar
Digital Library
- 14.D. Misunas. Petri Nets and Speed Independent Design. Communication of the ACM, 16, 1973. Google Scholar
Digital Library
- 15.B. Moszkowski. A Temporal Logic for Multilevel Reasoning About Hardware. IEEE Computer, February 1985.Google Scholar
Digital Library
- 16.L. W. Nagel. SPICE2: A Computer Program to Simulate Semiconductor Circuits. PhD thesis, UC Berkeley, May 1975.Google Scholar
- 17.M. Ram et al. Trace Theory and the Definition of Hierarchical Components. In Proceedings of the 3rd Caltech Conf. on VLSL Computer Science Press, 1983.Google Scholar
Cross Ref
- 18.D. Wallace and C. Sequin. Plug-In Timing Models for an Abstract Timing Verifier. In 23rd DAC, 1986. Google Scholar
Digital Library
Index Terms
CLOVER: a timing constraints verification system




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