ABSTRACT
Different sources of leakage can affect each other by interacting through resulting intermediate node voltages. This is known as the loading effect, In this paper, we propose a pattern dependent steady state leakage estimation technique that incorporates loading effect and addresses the three dominant sources of leakage, namely the sub-threshold, gate oxide and band-to-band tunneling leakages. We have developed a compact leakage model that supports iteration over node voltages based on Newton-Raphson method. The proposed estimation technique based on the compact model improves performance and capacity over SPICE. We report a speed up of 18,000X over SPICE. Results show that loading effect is a significant factor in leakage and worsens with technology scaling.
- International Roadmap for Semiconductor (ITRS)Google Scholar
- A. Rastogi, W. Chen, A. Sanyal, S. Kundu, "An Efficient Technique for Leakage Current Estimation in Sub 65nm Scaled CMOS Circuits Based on Loading Effect", Int. Conf. on VLSI Design 2007, Proc., pp. 583--588 Google Scholar
Digital Library
- S. Mukhopadhyay, A. Raychowdhury, K. Roy, "Accurate Estimation of Total Leakage Current in Scaled CMOS Logic Circuits Based on Compact Current Modeling," IEEE/ACM Design Automation Conf. 2003, Proc., pp. 169--174 Google Scholar
Digital Library
- S. Mukhopadhyay, S. Bhunia, K. Roy, "Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits," Design, Automation and Test in Europe 2005, Proc., pp. 224--229 Vol. 1 Google Scholar
Digital Library
- R. Brown, J. Burns, A. Devgan, R. Brown, "Efficient Techniques for Gate Leakage Estimation," Int. Symp. on Low Power Electronics and Design '03, Proc., pp. 100--103 Google Scholar
Digital Library
- C. Hu et al., "BSIM4 Gate Leakage Model Including Source-Drain Partition," International Electron Device Meeting 2000, pp. 815--818Google Scholar
- C. Hu et al., "BSIM4.5.0 Mosfet Model", User's Manual '04Google Scholar
- SIS: Logic Synthesis of Synchronous and Asynchronous Sequential Circuit program, UC BerkeleyGoogle Scholar
- D. Lee, D. Blaauw, D. Sylvester, "Gate Oxide Leakage Current Analysis and Reduction for VLSI Circuits", IEEE Trans. VLSI Systems, pp. 155--166 Vol. 12 Google Scholar
Digital Library
- R. Rao, A. Srivastava, D. Blaauw, D. Sylvester, "Statistical Analysis of Sub-threshold Leakage Current for VLSI Circuits", IEEE Trans. VLSI Systems, pp. 131--139 Google Scholar
Digital Library
- R. Bryant, "COSMOS: A Complied Simulator for MOS Circuits", Design Automation Conf. 1987, Proc., pp. 9--16 Google Scholar
Digital Library
Index Terms
On estimating impact of loading effect on leakage current in sub-65nm scaled CMOS circuits based on Newton-Raphson method
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