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On estimating impact of loading effect on leakage current in sub-65nm scaled CMOS circuits based on Newton-Raphson method

Published:04 June 2007Publication History

ABSTRACT

Different sources of leakage can affect each other by interacting through resulting intermediate node voltages. This is known as the loading effect, In this paper, we propose a pattern dependent steady state leakage estimation technique that incorporates loading effect and addresses the three dominant sources of leakage, namely the sub-threshold, gate oxide and band-to-band tunneling leakages. We have developed a compact leakage model that supports iteration over node voltages based on Newton-Raphson method. The proposed estimation technique based on the compact model improves performance and capacity over SPICE. We report a speed up of 18,000X over SPICE. Results show that loading effect is a significant factor in leakage and worsens with technology scaling.

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  1. On estimating impact of loading effect on leakage current in sub-65nm scaled CMOS circuits based on Newton-Raphson method

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    • Published in

      cover image ACM Conferences
      DAC '07: Proceedings of the 44th annual Design Automation Conference
      June 2007
      1016 pages
      ISBN:9781595936271
      DOI:10.1145/1278480

      Copyright © 2007 ACM

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      New York, NY, United States

      Publication History

      • Published: 4 June 2007

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      DAC '07 Paper Acceptance Rate152of659submissions,23%Overall Acceptance Rate1,770of5,499submissions,32%

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