Abstract
Real-time multimedia applications are increasingly being mapped onto MPSoC (multiprocessor system-on-chip) platforms containing hardware--software IPs (intellectual property), along with a library of common scheduling policies such as EDF, RM. The choice of a scheduling policy for each IP is a key decision that greatly affects the design's ability to meet real-time constraints, and also directly affects the energy consumed by the design. We present a cosynthesis framework for design space exploration that considers heterogeneous scheduling while mapping multimedia applications onto such MPSoCs. In our approach, we select a suitable scheduling policy for each IP such that system energy is minimized—our framework also includes energy-reduction techniques utilizing dynamic power management. Experimental results on a realistic multimode multimedia terminal application demonstrate that our approach enables us to select design points with up to 60.5% reduced energy for a given area constraint, while meeting all real-time requirements. More importantly, our approach generates a tradeoff space between energy and cost allowing designers to comparatively evaluate multiple system level mappings.
- Baruah, S. K. 2004. Cost efficient synthesis of real-time systems upon heterogeneous multiprocessor platforms. In WPDRTS '04: Proceedings of the 14th International Workshop on Parallel and Distributed Real-Time Systems. 120b.Google Scholar
Cross Ref
- Benini, L., Bogliolo, A., and Micheli, G. D. 2000. A survey of design techniques for system-level dynamic power management. IEEE Trans. Very Large Scale Integr. Syst. 8, 3, 299--316. Google Scholar
Digital Library
- Bijlsma, T., Wolkotte, P. T., and Smit, G. J. 2006. An optimal architecture for a DDC. In RAW '06: Proceedings of the 20th International Parallel & Distributed Processing Symposium Reconfigurable Architectures Workshop. Google Scholar
Digital Library
- Buttazzo, G. C. 2005. Rate monotonic vs. EDF: Judgment day. Real-Time Syst. 29, 1, 5--26. Google Scholar
Digital Library
- Fiduccia, C. M. and Mattheyses, R. M. 1982. A linear time heuristic for improved network partitions. In DAC '04: Proceedings of the 19th Annual Conference on Design Automation. 241--247. Google Scholar
Digital Library
- Flautner, K., Flynn, D., Roberts, D., and Patel, D. I. 2004. IEM926: An energy efficient SoC with dynamic voltage scaling. In DATE '04: Proceedings of the Design, Automation and Test in Europe Conference and Exposition. 324--329. Google Scholar
Digital Library
- Helmig, J. Texas Instruments, 2002. Developing Core Software Technologies for TI's OMAP Platform.Google Scholar
- Hill, S. 2001. The ARM10 family of advanced embedded microprocessor cores. In HotChips '01: A Symposium on High Performance Chips.Google Scholar
- Kernighan, B. W. and Lin, S. 1970. An efficient heuristic procedure for partitioning graphs. Bell Sys. Tech. J. 49, 2, 291--308.Google Scholar
Cross Ref
- Kim, M., Banerjee, S., Dutt, N., and Venkatasubramanian, N. 2006. Design space exploration of real-time multimedia MPSoCs with heterogeneous scheduling policies. In CODES+ISSS '06: Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis. 16--21. Google Scholar
Digital Library
- Liu, C. L. and Layland, J. W. 1973. Scheduling algorithms for multiprogramming in a hard-real-time environment. J. ACM 20, 1, 46--61. Google Scholar
Digital Library
- Marculescu, R., Nandi, A., Lavagno, L., and Sangiovanni-Vincentelli, A. L. 2001. System-level power/performance analysis of portable multimedia systems communicating over wireless channels. In ICCAD '01: Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design. 207--214. Google Scholar
Digital Library
- Matic, S. and Henzinger, T. A. 2005. Trading end-to-end latency for composability. In RTSS '05: Proceedings of the 26th IEEE International Real-Time Systems Symposium. 99--110. Google Scholar
Digital Library
- NXP. Nexperia Processor http://www.nxp.com/products/nexperia/home.Google Scholar
- Oh, H. and Ha, S. 1996. A static scheduling heuristic for heterogeneous processors. In Euro-Par '96: Proceedings of the Second International Euro-Par Conference on Parallel Processing-Volume II. 573--577. Google Scholar
Digital Library
- Oh, H. and Ha, S. 2002. Hardware-software cosynthesis of multimode multi-task embedded systems with real-time constraints. In CODES '02: Proceedings of the 10th International Symposium on Hardware/software Codesign. 133--138. Google Scholar
Digital Library
- Pham, D., Anderson, H.-W., Behnen, E., Bolliger, M., Gupta, S., Hofstee, P., Harvey, P., Johns, C., Kahle, J., Kameyama, A., Keaty, J., Le, B., Lee, S., Nguyen, T., Petrovick, J., Pham, M., Pille, J., Posluszny, S., Riley, M., Verock, J., Warnock, J., Weitzel, S., and Wendel, D. 2006. Key features of the design methodology enabling a multi-core soc implementation of a first-generation cell processor. In Proceedings of the Conference on Asia South Pacific Design Automation (ASP-DAC'06). 871--878. Google Scholar
Digital Library
- Pop, P., Eles, P., Peng, Z., and Pop, T. 2006. Analysis and optimization of distributed real-time embedded systems. ACM Trans. Des. Autom. Electron. Syst. 11, 3, 593--625. Google Scholar
Digital Library
- Schmitz, M. T., Al-Hashimi, B. M., and Eles, P. 2005. Cosynthesis of energy-efficient multimode embedded systems with consideration of mode-execution probabilities. IEEE Trans. on CAD of Integrated Circuits and Systems 24, 2, 153--169. Google Scholar
Digital Library
- Shin, I. and Lee, I. 2003. Periodic resource model for compositional real-time guarantees. In RTSS '03: Proceedings of the 24th IEEE International Real-Time Systems Symposium. 2--13. Google Scholar
Digital Library
- Shin, I. and Lee, I. 2004. Compositional real-time scheduling framework. In RTSS '04: Proceedings of the 25th IEEE International Real-Time Systems Symposium. 57--67. Google Scholar
Digital Library
- STMicroelectronics. ST Nomadik Multimedia Processor http://www.st.com/nomadik.Google Scholar
- Wolf, W. 2004. The future of multiprocessor systems-on-chips. In DAC '04: Proceedings of the 41st Annual Conference on Design Automation. 681--685. Google Scholar
Digital Library
- Yang, P., Wong, C., Marchal, P., Catthoor, F., Desmet, D., Verkest, D., and Lauwereins, R. 2001. Energy-aware runtime scheduling for embedded-multiprocessor SOCs. IEEE Des. Test 18, 5, 46--58. Google Scholar
Digital Library
Index Terms
Energy-aware cosynthesis of real-time multimedia applications on MPSoCs using heterogeneous scheduling policies
Recommendations
Design space exploration of real-time multi-media MPSoCs with heterogeneous scheduling policies
CODES+ISSS '06: Proceedings of the 4th international conference on Hardware/software codesign and system synthesisReal-time multi-media applications are increasingly being mapped onto MPSoC (multi-processor system-on-chip) platforms containing hardware-software IPs (intellectual property) along with a library of common scheduling policies such as EDF, RM. The ...
Analysis on quantum-based fixed priority scheduling of real-time tasks
ICUIMC '09: Proceedings of the 3rd International Conference on Ubiquitous Information Management and CommunicationFixed priority schedulers are widely used for real-time systems, and there were efforts to improve the schedulability. Preemption threshold scheduling is one of such efforts with a dual priority scheme. It increases the schedulability by introducing ...
Real-Time Job Scheduling in Hypercube Systems
ICPP '97: Proceedings of the international Conference on Parallel ProcessingIn this paper, we present the problem of scheduling real-time jobs in a hypercube system and propose a scheduling algorithm. The goals of the proposed scheduling algorithm are to determine whether all jobs can complete their processing before their ...






Comments