Abstract
A new method for improving the timing yield of field-programmable gate array (FPGA) devices affected by intrinsic within-die variation is proposed. The timing variation is reduced by selecting an appropriate configuration for each chip from a set of independent configurations, the critical paths of which do not share the same circuit resources on the FPGA. In this article, the actual method used to generate independent multiple configurations by simply repeating the routing phase is shown, along with the results of Monte Carlo simulation with 10,000 samples. One simulation result showed that the standard deviations of maximum critical path delays are reduced by 28% and 49% for 10% and 30% Vth variations (σ/ μ), respectively, with 10 independent configurations. Therefore, the proposed method is especially effective for larger Vth variation and is expected to be useful for suppressing the performance variation of FPGAs due to the future increase of parameter variation. Another simulation result showed that the effectiveness of the proposed technique was saturated at the use of 10 or more configurations because of the degradation of the quality of the configurations. Therefore, the use of 10 or fewer configurations is reasonable.
- Asenov, A., Brown, A. R., Davis, J. H., and Slavcheva, G. 2003. Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFET. IEEE Trans. Elect. Devi. 50, 9, 1837--1852.Google Scholar
Cross Ref
- Betz, V. and Rose, J. 1997. VPR: A new packing, placement and routing tool for FPGA research. In Proceedings of International Conference on Field-Programmable Logic and Applications, 213--222. Google Scholar
Digital Library
- Betz, V., Rose, J., and Marquardt, A. 1999. Architecture and CAD for deep-submicron FPGAs. Kluwer Academic Publishers, Norwell, MA. Google Scholar
Digital Library
- Betz, V. 2006. FPGA place-and-route challenge. http://www.eecg.toronto.edu/~vaughn/challenge/ challenge.html.Google Scholar
- Bowman, K. A., Tang, X. Eble, J., and Meindl, J. M. 2000. Impact of extrinsic and intrinsic parameter fluctuations on CMOS circuit performance. IEEE J. Solid-State Circ. 35, 8, 1186--1193.Google Scholar
Cross Ref
- Bowman, K. A., Duvall, S. G., and Meindl, J. M. 2002. Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration. IEEE J. Solid-State Circ. 37, 2, 183--190.Google Scholar
Cross Ref
- Campregher, N., Cheung, P., Constantinides, G., and Vasilko, M. 2006. Yield enhancements of design-specific FPGAs. In Proceedings of ACM/SIGDA International Symposium on Field-Programmable Gate Array. ACM, New York, 93--100. Google Scholar
Digital Library
- Cheng, L., Xiong, J., He, L., and Hutton, M. 2006. FPGA performance optimization via chipwise placement considering process variations. In Proceedings of International Conference on Field-Programmable Logic and Applications, 44--49.Google Scholar
- Cong, J. and Romesis, M. 2003. Optimality and stability study of timing-driven placement algorithm. In Proceedings of International Conference on Computer-Aided Design, 472--478. Google Scholar
Digital Library
- Friedberg, P., Cao, Y., Cain, J., Wang, R., Rabaey, J., and Spanos, C. 2005. Modeling within-field gate length spatial variation for process-design co-optimization, In Proceedings of Design and Process Integration for Microelectronic Manufacturing IV. SPIE, 5756, 178--188.Google Scholar
Cross Ref
- Hyder, Z. and Wawrzynek, J. 2005. Defect tolerance in multiple-FPGA Systems, In Proceedings of IEEE 15th International Conference on Field Programmable Logic and Application. IEEE Computer Society Press, Los Alamitos, CA, 24--26.Google Scholar
- ITRS 2005. Design Section.Google Scholar
- Katsuki, K., Kotani, M., Kobayashi, K., and Onodera, H. 2005. A yield and speed enhancement scheme under within-die variations on 90 nm LUT array. In Proceedings of IEEE Custom Integrated Circuit Conference. IEEE Computer Society Press, Los Alamitos, CA, 601--604.Google Scholar
- Krasniewski, A. 2003. Evaluation of testability of path delay faults for user-configured programmable devices. In Proceedings of International Conference on Field-Programmable Logic and Applications, 828--838.Google Scholar
Cross Ref
- Kuon, I. and Rose, J. 2006. Measuring the gap between FPGAs and ASICs. IEEE Trans. Computer-Aided Des. Integr. Circ. Syst. 26, 2, 203--215. Google Scholar
Digital Library
- Li, X., La, F., and Ling, T. 2004. FPGA as process monitor -- An effective method to characterize poly gate CD variation and its impact on product performance and yield. IEEE Trans. Semiconduct. Manufact. 17, 3, 267--272.Google Scholar
Cross Ref
- Lin, Y., Hutton, M., and He, L. 2006. Placement and timing for FPGAs considering variations. In Proceedings of International Conference on Field-Programmable Logic and Applications, 37--43.Google Scholar
- Matsumoto, Y., Hioki, M., Kawanami, T., Tsutsumi, T., Nakagawa, T., Sekigawa T., and Koike, H. 2007. Performance and yield enhancement of FPGAs with within-die variation using multiple configurations. In Proceedings of ACM/SIGDA International Symposium on Field-Programmable Gate Array. ACM, New York, 169--177. Google Scholar
Digital Library
- McMurchie, L. and Ebeling, C. 1995. PathFinder: A negotiation based performance driven router for FPGAs. In Proceedings of ACM/SIGDA International Symposium on Field-Programmable Gate Array. ACM, New York, 111--117. Google Scholar
Digital Library
- Menon, P. R., Xu, W., and Tessier, R. 2006. Design-specific path delay testing in lookup-table-based FPGAs. IEEE Trans. Computer-Aided Des. Integr. Circuits Syst. 25, 5, 867--877. Google Scholar
Digital Library
- Nabaa, G., Azizi, N., and Najm, F. N. 2006. An adaptive FPGA architecture with process variation compensation and reduced leakage. In Proceedings of Design Automation Conference, 624--629. Google Scholar
Digital Library
- Sedcole, P. and Cheung, P. Y. K. 2006. Within-die delay variability in 90 nm FPGAs and beyond. In Proceedings of IEEE International Conference on Field-Programmable Technology. IEEE Computer Society Press, Los Alamitos, CA, 97--104.Google Scholar
- Srinivasan, S. and Narayanan, V. 2006. Variation aware placement for FPGAs. In Proceedings of IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures. IEEE Computer Society Press, Los Alamitos, CA, 422--423. Google Scholar
Digital Library
- STARC 2006. http://www.starc.jp/index-e.htmlGoogle Scholar
- Watts, J., Lu, N., Bittner, C., Grundon, S., and Oppold, J. 2005. Modeling FET variation within a chip as a function of circuit design and layout choices. In Proceedings of the Nanotech Workshop on Compact Modeling, 87--92.Google Scholar
- Wong, P., Cheng, L., Lin, Y., and He, L. 2005. FPGA device and architecture evaluation considering process variation. In Proceedings of International Conference on Computer-Aided Design, 29--24. Google Scholar
Digital Library
- Xilinx, Inc. 2005. EasyPath Devices Data Sheet.Google Scholar
Index Terms
Suppression of Intrinsic Delay Variation in FPGAs using Multiple Configurations
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