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Statistical Analysis and Process Variation-Aware Routing and Skew Assignment for FPGAs

Published:17 March 2008Publication History
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Abstract

With constant scaling of process technologies, chip design is becoming increasingly difficult due to process variations. The FPGA community has only recently started focusing on the effects of variations. In this work we present a statistical analysis to compare the effects of variations on designs mapped to FPGAs and ASICs. We also present CAD and architecture techniques to mitigate the impact of variations. First we present a variation-aware router that optimizes statistical criticality. We then propose a modification to the clock network to deliver programmable skews to different flip-flops. Finally, we combine the two techniques and the result is a 9x reduction in yield loss that translates to a 12% improvement in timing yield. When the desired timing yield is set to 99%, our combined statistical routing and skew assignment technique results in a delay improvement of about 10% over a purely deterministic approach.

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    • Published in

      cover image ACM Transactions on Reconfigurable Technology and Systems
      ACM Transactions on Reconfigurable Technology and Systems  Volume 1, Issue 1
      Special edition on the 15th international symposium on FPGAs
      March 2008
      139 pages
      ISSN:1936-7406
      EISSN:1936-7414
      DOI:10.1145/1331897
      Issue’s Table of Contents

      Copyright © 2008 ACM

      Publisher

      Association for Computing Machinery

      New York, NY, United States

      Publication History

      • Published: 17 March 2008
      • Accepted: 1 December 2007
      • Revised: 1 October 2007
      • Received: 1 May 2007
      Published in trets Volume 1, Issue 1

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