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Designing Efficient Input Interconnect Blocks for LUT Clusters Using Counting and Entropy

Published:17 March 2008Publication History
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Abstract

In a cluster-based FPGA, the interconnect from external routing tracks and cluster feedbacks to the LUT inputs consumes significant area, and no consensus has emerged among different implementations (e.g., 1-level or 2-level). In this paper, we model this interconnect as a unified input interconnect block (IIB). We identify three types of IIBs and develop general combinatorial techniques to count the number of distinct functional configurations for them. We use entropy, defined as the logarithm of this count, to estimate an IIB's routing flexibility. This enables us to analytically evaluate different IIBs without the customary time-consuming place and route experiments. We show that both depopulated 1-level IIBs and VPR-style 2-level IIBs achieve high routing flexibility but lack area efficiency. We propose a novel class of highly efficient, yet still simple, IIBs that use substantially fewer switches with only a small degradation in routing flexibility. Experimental results verify the routability of these IIBs, and confirm that entropy is a good predictor of routability.

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  1. Designing Efficient Input Interconnect Blocks for LUT Clusters Using Counting and Entropy

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    • Published in

      cover image ACM Transactions on Reconfigurable Technology and Systems
      ACM Transactions on Reconfigurable Technology and Systems  Volume 1, Issue 1
      Special edition on the 15th international symposium on FPGAs
      March 2008
      139 pages
      ISSN:1936-7406
      EISSN:1936-7414
      DOI:10.1145/1331897
      Issue’s Table of Contents

      Copyright © 2008 ACM

      Publisher

      Association for Computing Machinery

      New York, NY, United States

      Publication History

      • Published: 17 March 2008
      • Accepted: 1 December 2007
      • Revised: 1 September 2007
      • Received: 1 May 2007
      Published in trets Volume 1, Issue 1

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