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A Synthesizable Datapath-Oriented Embedded FPGA Fabric for Silicon Debug Applications

Published:17 March 2008Publication History
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Abstract

We present an architecture for a synthesizable datapath-oriented FPGA core that can be used to provide post-fabrication flexibility to an SoC. Our architecture is optimized for bus-based operations and employs a directional routing architecture, which allows it to be synthesized using standard ASIC design tools and flows. The primary motivation for this architecture is to provide an efficient mechanism to support on-chip debugging. The fabric can also be used to implement other datapath-oriented circuits such as those needed in signal processing and computation-intensive applications. We evaluate our architecture using a set of benchmark circuits and compare it to previous fabrics in terms of area, speed, and power.

References

  1. Abramovici, M., Bradley, P., Dwarakanath, K., Levin, P., Memmi, G., and Miller, D. 2006. A reconfigurable design-for-debug infrastructure for SoCs. In Proceedings of the ACM IEEE Design Automation Conference. ACM, New York, 7--12. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. Abramovici, M., Stroud, C., and Emmert, M. 2002. Using embedded FPGAs for SoC yield improvement. In Proceedings of the Design Automation Conference. 713--724. Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. Chen, D., Cong, J., Ercegovac, M., and Huang, Z. 2001. Performance-driven mapping for CPLD architectures. In Proceedings of the ACM International Symposium on Field-Programmable Gate Arrays. ACM, New York, 39--47. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. Cherepacha, D. and Lewis, D. 1996. DP-FPGA: An FPGA architecture optimized for datapaths. In Proceedings of the International Conference on VLSI Design. 329--343.Google ScholarGoogle Scholar
  5. Compton, K. and Hauck, S. 2007. Automatic design of area-efficient configurable ASIC cores. IEEE Trans. Comput. 56, 5 (May), 662--672. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. Cronquist, D., Franklin, P., Fisher, C., Figueroa, M., and Ebeling, C. 1999. Architecture design of reconfigurable pipelined datapaths. In Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI. 23--40. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. Fletcher, J. 1982. An arithmetic checksum for serial transmissions. IEEE Trans. Commun. COM-30, 1 (Jan), 247--252.Google ScholarGoogle ScholarCross RefCross Ref
  8. Goldstein, S., Schmit, H., Budiu, M., Cadambi, S., Moe, M., and Taylor, R. 2000. Piperench: A reconfigurable architecture and compiler. IEEE Comput. 33, 4 (Apr), 70--77. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. Hauck, S., Fry, T., Hosler, M., and Kao, J. 2004. The Chimera Reconfigurable functional unit. IEEE Trans. VLSI 12, 2 (Feb.), 206--217. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. Ho, C., Leong, P., Luk, W., Wilton, S., and Lopez-Buedo, S. 2006. Virtual embedded blocks: A methodology for evaluating embedded elements in FPGAs. In Proceedings of the International Symposium on Field-Programmable Custom Computing Machines. 35--44. Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. Holland, M. and Hauck, S. 2007. Automatic creation of domain-specific reconfigurable CPLD for SoC. IEEE Trans. Comput.-Aid. Des. Integrat. Circ. Syst. 26, 2 (Feb), 291--295. Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. Kuon, I. and Rose, J. 2007. Measuring the gap between FPGAs and ASICs. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 26, 2 (Feb), 203--215. Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. Leijten-Nowak, K. and van Meerbergen, J. L. 2003. An FPGA architecture with enhanced datapath functionality. In Proceedings of the International Symposium on Field-Programmable Gate Arrays. 195--204. Google ScholarGoogle ScholarDigital LibraryDigital Library
  14. Marshall, A., Stansfield, T., Kostarnov, I., Vuillemin, J., and Hutchings, B. 1999. A reconfigurable arithmetic array for multimedia applications. In Proceedings of the ACM International Symposium on Field-Programmable Gate Arrays. ACM, New York, 135--143. Google ScholarGoogle ScholarDigital LibraryDigital Library
  15. Menezes, A., van Oorschot, P., and Vanstone, S. 1996. Handbook of Applied Cryptography. CRC Press, 602--606. Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. Nakassis, T. 1988. Fletcher's error detection algorithm: How to implement it efficiently and how to avoid the most common pitfalls. ACM Comput. Commun. Rev. 18, 5 (Oct), 86--94. Google ScholarGoogle ScholarDigital LibraryDigital Library
  17. Padalia, K., Fung, R., Bourgeault, M., Egier, A., and Rose, J. 2003. Automatic transistor and physical design of FPGA tiles from an architecture specification. In Proceedings of the ACM International Conference on FPGAs. ACM, New York, 164--172. Google ScholarGoogle ScholarDigital LibraryDigital Library
  18. Quinton, B. and Wilton, S. 2005. Post-silicon debug using programmable logic cores. In Proceedings of the International Conference on Field-Programmable Technology. 241--247.Google ScholarGoogle Scholar
  19. Sarangi, S., Narayanasamy, S., Carneal, B., Tiwari, A., Calder, B., and Torrellas, J. 2007. Patching processor design errors with programmable hardware. IEEE Micro 27, 1 (Jan-Feb), 12--25. Google ScholarGoogle ScholarDigital LibraryDigital Library
  20. Sarangi, S., Tiwari, A., and Torrellas, J. 2006. Pheonix: Detecting and recovering from permanent processor design bugs with programmable hardware. In Proceedings of the IEEE/ACM International Symposium on Microarchitecture. ACM, New York, 26--37. Google ScholarGoogle ScholarDigital LibraryDigital Library
  21. Singh, H., Lee, M., Lu, G., Kurdahi, F., Bagherzadeh, N., and Chaves, E. 2000. Morphosys: An integrated reconfigurable system for data-parallel and compute intensive applications. IEEE Trans. Comput. 49, 5 (April), 465--481. Google ScholarGoogle ScholarDigital LibraryDigital Library
  22. Wagner, I., Bertacco, V., and Austin, T. 2006. Shielding against design flaws with field repairable control logic. In Proceedings of the Design Automation Conference. 344--347. Google ScholarGoogle ScholarDigital LibraryDigital Library
  23. Wilton, S., Ho, C., Leong, P. H., Luk, W., and Quinton, B. 2007. A synthesizable datapath-oriented embedded fpga fabric. In Proceedings of the ACM International Symposium on Field-Programmable Gate Arrays. ACM, New York, 33--41. Google ScholarGoogle ScholarDigital LibraryDigital Library
  24. Wilton, S., Kafafi, N., Wu, J., Bozman, K., Aken'Ova, V., and Saleh, R. 2005. Design considerations for soft embedded programmable logic cores. IEEE J. Solid-State Circ. 40, 2 (Feb.), 485--497.Google ScholarGoogle ScholarCross RefCross Ref
  25. Yan, A. and Wilton, S. 2006. Product-term based synthesizable embedded programmable logic cores. IEEE Trans. VLSI 14, 5 (May), 474--488. Google ScholarGoogle ScholarDigital LibraryDigital Library
  26. Ye, A. and Rose, J. 2005. Using bus-based connections to improve field-programmable gate array density for implementing datapath circuits. In Proceedings of the International Symposium on Field-Programmable Gate Arrays. 3--13. Google ScholarGoogle ScholarDigital LibraryDigital Library
  27. Ye, A., Rose, J., and Lewis, D. 2003. Architecture of datapath-oriented coarse-grain logic and routing for FPGAs. In Proceedings of the IEEE Custom Integrated Circuits Conference. IEEE Computer Society Press, Los Alamitos, CA, 61--64.Google ScholarGoogle Scholar

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    • Published in

      cover image ACM Transactions on Reconfigurable Technology and Systems
      ACM Transactions on Reconfigurable Technology and Systems  Volume 1, Issue 1
      Special edition on the 15th international symposium on FPGAs
      March 2008
      139 pages
      ISSN:1936-7406
      EISSN:1936-7414
      DOI:10.1145/1331897
      Issue’s Table of Contents

      Copyright © 2008 ACM

      Publisher

      Association for Computing Machinery

      New York, NY, United States

      Publication History

      • Published: 17 March 2008
      • Accepted: 1 December 2007
      • Revised: 1 September 2007
      • Received: 1 May 2007
      Published in trets Volume 1, Issue 1

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