The amorphous FPGA architecture

ABSTRACT

This paper describes the Amorphous FPGA, an innovative architecture attempting to optimally allocate logic and routing resource on per-mapping basis. Designed for high performance, routability, and ease-of-use, it supports variable-granularity logic blocks, dedicated wide multiplexers, and variable-length bypassing interconnects with a symmetrical structure. Due to its many unconventional architectural features, the amorphous FPGA requires several major modifications to be made in the standard VPR placement/routing CAD flow, which include a new placement algorithm and a modified delay-based routing procedure. It is shown that, on average, an FPGA with the amorphous architecture can achieve a 1.35 times improvement in logic density, 9% improvement in average net delay, and 4% improvement in the critical-path delay for the largest 20 MCNC benchmark circuits over an island-style baseline

References

1. A. Dehon, "Nanowire-based programmable architectures," J. Emerg. Technol. Comput. Syst., vol 1, no2, pp109--162, 2005.
2. I. Kuon and J. Rose, "Measuring the gap between FPGAs and ASICs," in Proceedings of the 2006 ACM/SIGDA Tenth International Symposium on FPGA, pp21--30, 2006.
3. A. DeHon, "Balancing interconnect and computation in a reconfigurable computing array," in Proceedings of the ACM/SIGDA 7th international symposium on Field programmable gate arrays, 1999.
4. G. Borriello, C. Ebeling, S.A. Hauck, and S. Burns, "The triptych FPGA architecture," IEEE Trans. Very Large Scale Integr. Syst., vol 3, no4, 1995.
5. M. Tom and G. Lemieux, "Logic block clustering of large designs for channel-width constrained fpgas," in DAC'05: Proceedings of the 42nd annual conference on Design automation, pp726--731, ACM, 2005.
6. D.B. Strukov and K.K. Likharev, "A reconfigurable architecture for hybrid CMOS/Nanodevice circuits," in Proceedings of the 2006 ACM/SIGDA 14th international symposium on FPGA, pp131--140, 2006.
7. Actel, Inc., "Automotive ProASIC3 flash family FPGAs datasheet," March 2007.
8. Xilinx, "Virtex-II Pro/Virtex-II Pro X complete data sheet (all four modules)," March 2007.
9. D. Lewis, E. Ahmed, G. Baeckler, V. Betz, M. Bourgeault, D. Cashman, D. Galloway, M. Hutton, C. Lane, A. Lee, P. Leventis, S. Marquardt, C. McClintock, K. Padalia, B. Pedersen, G. Powell, B. Ratchev, S. Reddy, J. Schleicher, K. Stevens, R. Yuan, R. Cliff, and J. Rose, "The stratix II logic and routing architecture," in Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays, pp14--20, 2005.
10. E. Ahmed and J. Rose, "The effect of LUT and cluster size on deep-submicron FPGA performance and density," in the 2000 International Symposium on FPGA, Feb. 2000.
11. D. Hill and N.-S. Woo, "The benefits of flexibility in lookup table-based FPGAs," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol12, pp349--353, Feb. 1993.
12. J. He and J. Rose, "Advantages of heterogeneous logic block architectures for FPGAs," in Proc. IEEE Custom Integr. Circuits Conf., pp741--745, 1993.
13. M. Hutton, J. Schleicher, D.M. Lewis, B. Pedersen, R. Yuan, S. Kaptanoglu, G. Baeckler, B. Ratchev, K. Padalia, M. Bourgeault, A. Lee, H. Kim, and R. Saini, "Improving FPGA performance and area using an adaptive logic module.," in FPL, pp135--144, 2004.
14. V. Betz and J. Rose, "FPGA routing architecture: segmentation and buffering to optimize speed and density," in Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on FPGA, pp59--68, 1999.
15. M. Lin, A. El Gamal, Y.-C. Lu, and S. Wong, "Performance benefits of monolithically stacked 3D-FPGA," in Proceedings of the 2006 International Symposium on FPGA, pp113--122, 2006.
16. L. Ciccarelli, D. Loparco, M. Innocenti, A. Lodi, C. Mucci, and P. Rolandi, "A low-power routing architecture optimized for deep sub-micron FPGAs," in Conference 2006, IEEE Custom Integrated Circuits, pp309--312, 10-13 Sept. 2006.
17. M. Pedram, B. Nobandegani, and B. Preas, "Design and analysis of segmented routing channels for row-based FPGAs," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol 13, pp1470--1479, Dec. 1994.
18. J.R. Hauser and J. Wawrzynek, "Garp: a MIPS processor with a reconfigurable coprocessor," in Proceedings of the 5th IEEE Symposium on FCCM, p12, 1997.
19. N. Weaver, J. Hauser, and J. Wawrzynek, "The SFRA: a corner-turn FPGA architecture," in Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays, pp3--12, 2004.
20. O. Agrawal, H. Chang, B. Sharpe-Geisler, N. Schmitz, B. Nguyen, J. Wong, G. Tran, F. Fontana, and B. Harding, "An innovative, segmented high performance FPGA family with variable-grain-architecture and wide-gating functions," in Proceedings of the 1999 international symposium on FPGA, pp17--26, 1999.
21. Xilinx, "The 40% performance advantage of Virtex-II Pro FPGAs over Competitive PLDs." White paper by Xilinx Inc., 2006.
22. Xilinx, "Achieve higher system performance with the Virtex-5 Family of FPGAs." White paper by Xilinx Inc., 2006.
23. V.M.K. Kamal Chaudhary, Philip DCostello, "Programmable circuit optionally configurable as a lookup table or a wide multiplexer," July 2006.
24. P. Metzgen and D. Nancekievill, "Multiplexer restructuring for FPGA implementation cost reduction," in Design Automation Conference, 2005. Proceedings. 42nd, pp421--426, 13-17 June 2005.
25. V. Betz and J. Rose, "VPR: A new packing, placement and routing tool for FPGA research," in Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications, pp213--222, 1997.
26. C. Li, M. Xie, C.-K. Koh, J. Cong, and P.H. Madden, "Routability-driven placement and white space allocation," in ICCAD'04: Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, (Washington, DC, USA), pp394--401, IEEE Computer Society, 2004.
27. B.-KC. X. Yang and M. Sarrafzadeh, "Routability-driven white space allocation for fixed-die standard-cell placement," IEEE Trans. on CAD, vol 22, pp410--419, April 2003.
28. A. Kahng and G. Robins, "A new class of iterative steiner tree heuristics with good performance," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol 11, pp893--902, July 1992.
29. C. Ebeling, L. McMurchie, S. Hauck, and S. Burns, "Placement and routing tools for the Triptych FPGA," IEEE Trans. Very Large Scale Integr. Syst., vol 3, no 4, pp473--482, 1995.
30. M. Lin, A. El Gamal, Y.-C. Lu, and S. Wong, "Performance benefits of monolithically stacked 3-D FPGA," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol 26, pp216--229, Feb. 2007.
31. Y. Cao, T. Sato, M. Orshansky, D. Sylvester, and C. Hu, "New paradigm of predictive mosfet and interconnect modeling for early circuit simulation," in Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000, pp201--204, 2000.
32. G. Lemieux and D. Lewis, "Circuit design of routing switches," in Proceedings of the 2002 ACM/SIGDA Tenth International Symposium on Field-Programmable Gate Arrays, pp19--28, 2002.
33. V. Betz, J. Rose, and A. Marquardt, eds., Architecture and CAD for Deep-Submicron FPGAs. Norwell, MA, USA: Kluwer Academic Publishers, 1999.

Index Terms

• Hardware

  • Integrated circuits

    • Logic circuits

  • Very large scale integration design

    • Application-specific VLSI designs