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SoftSig: software-exposed hardware signatures for code analysis and optimization

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Published:01 March 2008Publication History

ABSTRACT

Many code analysis techniques for optimization, debugging, or parallelization need to perform runtime disambiguation of sets of addresses. Such operations can be supported efficiently and with low complexity with hardware signatures.

To enable flexible use of signatures, this paper proposes to expose a Signature Register File to the software through a rich ISA. The software has great flexibility to decide, for each signature,which addresses to collect and which addresses to disambiguate against. We call this architecture SoftSig. In addition, as an example of SoftSig use, we show how to detect redundant function calls efficiently and eliminate them dynamically. We call this algorithm MemoiSE. On average for five popular applications, MemoiSE reduces the number of dynamic instructions by 9.3%, thereby reducing the execution time of the applications by 9%.

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References

  1. D. Bernstein, D. Cohen, and D. E. Maydan, "Dynamic Memory Disambiguation for Array References," in International Symposium on Microarchitecture, November 1994. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. B. Bloom, "Space/Time Trade-Offs in Hash Coding with Allowable Errors," Communications of the ACM, vol. 11, July 1970. Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. L. Ceze, J. Tuck, C. Cascaval, and J. Torrellas, "Bulk Disambiguation of Speculative Threads in Multiprocessors," in International Symposium on Computer Architecture, June 2006. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. L. Ceze, J. Tuck, P. Montesinos, and J. Torrellas, "BulkSC: Bulk Enforcement of Sequential Consistency," in International Symposium on Computer Architecture, June 2007. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. D. A. Connors, H. C. Hunter, B.-C. Cheng, and W.-M. W. Hwu, "Hardware Support for Dynamic Activation of Compiler-Directed Computation Reuse," in International Conference on Architectural Support for Programming Languages and Operating Systems, November 2000. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. D. A. Connors and W.-M. W. Hwu, "Compiler-Directed Dynamic Computation Reuse: Rationale and Initial Results," in International Symposium on Microarchitecture, November 1999. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. T. H. Cormen, C. E. Leiserson, R. L. Rivest, and C. Stein, Introduction to Algorithms. MIT Press, Cambridge, MA, 2001. Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. Y. Ding and Z. Li, "A Compiler Scheme for Reusing Intermediate Computation Results," in International Symposium on Code Generation and Optimization, March 2004. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. D. M. Gallagher, W. Y. Chen, S. A. Mahlke, J. C. Gyllenhaal, and W.-M. W. Hwu, "Dynamic Memory Disambiguation Using the Memory Conflict Buffer," in International Conference on Architectural Support for Programming Languages and Operating Systems, October 1994. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. J. Huang and D. Lilja, "Exploiting Basic Block Value Locality with Block Reuse," in International Symposium on High Performance Computer Architecture, January 1999. Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. Intel Corporation, Intel 64 and IA-32 Architectures Software Developer's Manual. Volume 3B: System Programming Guide, Part II, November 2007.Google ScholarGoogle Scholar
  12. V. Krishnan and J. Torrellas, "A Chip-Multiprocessor Architecture with Speculative Multithreading," IEEE Trans. on Computers, September 1999. Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. J. Lin, T. Chen, W.-C. Hsu, and P.-C. Yew, "Speculative Register Promotion Using Advanced Load Address Table (ALAT)," in International Symposium on Code Generation and Optimization, March 2003. Google ScholarGoogle ScholarDigital LibraryDigital Library
  14. M. Lipasti, C.Wilkerson, and J. Shen, "Value Locality and Load Value Prediction," in International Conference on Architectural Support for Programming Languages and Operating Systems, October 1996. Google ScholarGoogle ScholarDigital LibraryDigital Library
  15. M. H. Lipasti and J. P. Shen, "Exceeding the Dataflow Limit Via Value Prediction," in International Symposium on Microarchitecture, December 1996. Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. C.-K. Luk, R. Cohn, R. Muth, H. Patil, A. Klauser, G. Lowney, S.Wallace, V. J. Reddi, and K. Hazelwood, "Pin: Building Customized Program Analysis Tools with Dynamic Instrumentation," in International Conference on Programming Language Design and Implementation, June 2005. Google ScholarGoogle ScholarDigital LibraryDigital Library
  17. D. Michie, ""Memo" Functions and Machine Learning," in Nature, April 1968.Google ScholarGoogle Scholar
  18. C. C. Minh et al., "An Effective Hybrid Transactional Memory System with Strong Isolation Guarantees," in International Symposium on Computer Architecture, June 2007. Google ScholarGoogle ScholarDigital LibraryDigital Library
  19. A. Moshovos, G. Memik, A. Choudhary, and B. Falsafi, "JETTY: Filtering Snoops for Reduced Energy Consumption in SMP Servers," in International Symposium on High-Performance Computer Architecture, January 2001. Google ScholarGoogle ScholarDigital LibraryDigital Library
  20. N. Neelakantam, R. Rajwar, S. Srinivas, U. Srinivasan, and C. Zilles, "Hardware Atomicity for Reliable Software Speculation," in International Symposium on Computer Architecture, June 2007. Google ScholarGoogle ScholarDigital LibraryDigital Library
  21. J.-K. Peir, S.-C. Lai, S.-L. Lu, J. Stark, and K. Lai, "Bloom Filtering Cache Misses for Accurate Data Speculation and Prefetching," in International Conference on Supercomputing, June 2002. Google ScholarGoogle ScholarDigital LibraryDigital Library
  22. M. Postiff, D. Greene, and T. Mudge, "The Store-load Address Table and Speculative Register Promotion," in International Symposium on Microarchitecture, December 2000. Google ScholarGoogle ScholarDigital LibraryDigital Library
  23. J. Renau, B. Fraguela, J. Tuck, W. Liu, M. Prvulovic, L. Ceze, S. Sarangi, P. Sack, K. Strauss, and P. Montesinos, "SESC Simulator," January 2005. http://sesc.sourceforge.net.Google ScholarGoogle Scholar
  24. S. Sastry, R. Bodik, and J. Smith, "Characterizing Coarse-Grained Reuse of Computation," in Workshop on Feedback-Directed and Dynamic Optmization, 2000.Google ScholarGoogle Scholar
  25. S. Sethumadhavan, R. Desikan, D. Burger, C. Moore, and S. Keckler, "Scalable Hardware Memory Disambiguation for High ILP Processors," in International Symposium on Microarchitecture, December 2003. Google ScholarGoogle ScholarDigital LibraryDigital Library
  26. A. Sodani and G. S. Sohi, "Dynamic Instruction Reuse," in International Symposium on Computer Architecture, June 1997. Google ScholarGoogle ScholarDigital LibraryDigital Library
  27. A. Sodani and G. S. Sohi, "An Empirical Analysis of Instruction Repetition," in International Conference on Architectural Support for Programming Languages and Operating Systems, October 1998. Google ScholarGoogle ScholarDigital LibraryDigital Library
  28. G. Sohi, S. Breach, and T. Vijayakumar, "Multiscalar Processors," in International Symposium on Computer Architecture, June 1995. Google ScholarGoogle ScholarDigital LibraryDigital Library
  29. B. Su, S. Habib, W. Zhao, J. Wang, and Y. Wu, "A Study of Pointer Aliasing for Software Pipelining Using Run-time Disambiguation," in International Symposium on Microarchitecture, November 1994. Google ScholarGoogle ScholarDigital LibraryDigital Library
  30. Y. Wu, D.-Y. Chen, and J. Fang, "Better Exploration of Region level Value Locality with Integrated Computation Reuse and Value Prediction," in International Symposium on Computer Architecture, June 2001. Google ScholarGoogle ScholarDigital LibraryDigital Library
  31. L. Yen et al., "LogTM-SE: Decoupling Hardware Transactional Memory from Caches," in International Symposium on High Performance Computer Architecture, February 2007. Google ScholarGoogle ScholarDigital LibraryDigital Library

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  1. SoftSig: software-exposed hardware signatures for code analysis and optimization

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