Abstract
Most of the work done in the field of code compression pertains to processors with fixed-length instruction encoding. The design of a code-compression scheme for variable-length instruction encodings poses newer design challenges. In this work, we first investigate the scope for code compression on variable-length instruction-set processors whose encodings are already optimized to a certain extent with respect to their usage. For such ISAs instruction boundaries are not known prior to decoding. Another challenging task of designing a code-compression scheme for such ISAs is designing the decompression hardware, which must decompress code postcache so that we gain in performance. We present two dictionary-based code compression schemes. The first algorithm uses a bit-vector; the second one uses reserved instructions to identify code words. We design additional logic for each of the schemes to decompress the code on-the-fly. We test the two algorithms with a variable-length RISC processor. We provide a detailed experimental analysis of the empirical results obtained by extensive simulation-based design space exploration for this system. The optimized decompressor can now execute compressed program faster than the native program. The experiments demonstrate reduction in code size (up to 30%), speed-up (up to 15%), and bus-switching activity (up to 20%). We also implement one decompressor in a hardware description language and synthesize it to illustrate the small overheads associated with the proposed approach.
- Araujo, G., Centoducatte, P., Cortes, M., and Pannain, R. 1998. Code compression based on operand factorization. In Proceedings of 31st Annual ACM/IEEE International Symposium on Microarchitecture (Micro). IEEE Computer Society Press, Los Alamitos, CA. 194--201. Google Scholar
Digital Library
- Arm. 1995. ARM7TDMI Data Sheet, Document Number: ARM DDI 0029E, Advanced RISC Machines.Google Scholar
- Beszédes, Á., Ferenc, R., Gyimóthy, T., Dolenc, A., and Karsisto, K. 2003. ACM Comput. Surv. 35, 3, 223--267. Google Scholar
Digital Library
- Burger, D. and Austin, T. M. 1997. The SimpleScalar Toolset, Ver. 2.0. Comput. Arch. News 25, 3 (June), 13--25. Google Scholar
Digital Library
- Cooper, K. and Mc Intosh, N. 1999. Enhanced code compression for embedded RISC processors. In Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI). ACM Press, New York. 139--149. Google Scholar
Digital Library
- Corliss, M., Christopher Lewis, E., and Amir R. 2005. The Implementation and Evaluation of Dynamic Code Decompression using DISE. ACM Trans. Embedded Comput. Syst. 4, 1, 38--72. Google Scholar
Digital Library
- Das, D., Kumar, R., and Chakrabarti, P.P. 2005. Dictionary based code compression for variable length instruction encodings. In Proceedings of the VLSI Design Conference. IEEE Computer Society Press, Los Alamitos, CA. 545--550. Google Scholar
Digital Library
- Debray, S.K. and Evans, W. 2002. Profile-guided code compression. In Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI). ACM Press, New York. 95--105. Google Scholar
Digital Library
- Debray, S.K., Evans, W., Muth, R., and De Sutter, B. 2000. Compiler techniques for code compaction. ACM Trans. Programming Languages Syst. 22, 2, 378--415. Google Scholar
Digital Library
- De Sutter, B., De Bus, B., and De Bosschere, K. 2002. Sifting out the mud: Low level C++ code reuse. In Proceedings of the ACM SIGPLAN Conference on Object-Oriented Programming, Systems, Languages and Applications (OOPSLA). ACM Press, New York. 275--291. Google Scholar
Digital Library
- De Sutter, B., De Bus, B., Vandierendonck, H., and De Bosschere, K. 2003. On the side-effects of code abstraction. In Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers and Tools for Embedded Systems (LCTES). ACM Press, New York. 244--253. Google Scholar
Digital Library
- Gaffney, J. E. 1984. Instruction entropy—a possible measure of program/architecture compatibility. ACM SIGMETERICS 12, 4, 13--18. Google Scholar
Digital Library
- Guthaus, M. R., Ringenberg, J. S., Ernst, D., Austin T. M., Mudge, T., and Brown, R. B. 2001. MiBench: A free, commercially representative embedded benchmark suite. In IEEE 4th Annual Workshop on Workload Characterization (Dec.) Austin, TX. {http://www.eecs.umich.edu/mibench/} Google Scholar
Digital Library
- IBM 1998. CodePack: PowerPC Code Compression Utility User's Manual Version 3.0. IBM Corporation.Google Scholar
- Inshiura, N. and Yamaguchi, M. 1997. Instruction code compression for application specific VLIW processors based on automatic field partitioning. In Proceedings of the Workshop on Synthesis and System Integration of Mixed Technologies. 105--109.Google Scholar
- Kemp, T. M., Montoye, R. K., Haper, J. D., Palmer, J. D., and Auerbach, D. J. 1998. A decompression core for PowerPC. IBM J. Res. Develop. 42, 6, 807--812. Google Scholar
Digital Library
- Kissel, K. 1997. High-density MIPS for the embedded market. Silicon Graphics MIPS Group. http://mips.com.Google Scholar
- Krishnaswamy, A. and Gupta, R. 2003. Enhancing the performance of 16 bit code using augmenting instructions. In Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers and Tools for Embedded Systems (LCTES). ACM Press, New York. 254--264. Google Scholar
Digital Library
- Lefurgy, C. 2000. Efficient execution of compressed programs. PhD dissertation, University of Michigan. Google Scholar
Digital Library
- Lefurgy, C. R., Bird, P. L., Chen, I. C., and Mudge, T. N. 1997. Improving code density using compression techniques. In Proceedings of the 30th ACM/IEEE International Symposium on Microarchitecture (Micro), IEEE Computer Society Press, Los Alamitos, CA. 194--203. Google Scholar
Digital Library
- Lefurgy, C. R., Piccininni, E., and Mudge, T. N. 2000. Reducing code size with run-time decompression. In Proceedings of the 6th International Symposium on High-Performance Computer Architecture (HPCA). IEEE Computer Society Press, Los Alamitos, CA. 218--228.Google Scholar
- Lekatsas, H. and Wolf, W. 1998. Code compression for embedded systems. In Proceedings of the ACM/IEEE Design Automation Conference (DAC). ACM Press, New York. 516--521. Google Scholar
Digital Library
- Lekatsas, H., and Wolf, W. 1999. SAMC: A code compression algorithm for embedded processors. IEEE Trans. CAD 18, 12 (Dec.), 1689--1701. Google Scholar
Digital Library
- Lekatsas, H., Henkel, J., and Wolf, W. 2000. Code compression for low power embedded system design. In Proceedings of the ACM/IEEE Design Automation Conference (DAC). ACM Press, New York. 430--439. Google Scholar
Digital Library
- Lekatsas, H., Henkel, J., Jakkula, V., and Chakradhar, S. T. 2005. A unified architecture for adaptive compression of data and code on embedded systems. In Proceedings of the VLSI Design Conference IEEE Computer Society Press, Los Alamitos, CA. 117--123. Google Scholar
Digital Library
- Liao, S., Devadas, S., and Keutzer, K. 1995. Code density optimization for embedded DSP processors using data compression techniques. In Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'). IEEE Computer Society Press, Los Alamitos, CA. 272--278. Google Scholar
Digital Library
- Liao, S., Devadas, S., and Keutzer, K. 1999. A text compression method for code-size minimization in embedded systems. ACM Trans. Design Auto. Electronic Syst. 4, 1, 12--38. Google Scholar
Digital Library
- Nam, S.J., Park, I.C., and Kyung, C.M. 1999. Improving dictionary-based code compression for VLIW architectures. IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. 2318--2324.Google Scholar
- National Semiconductor Inc. 2002. CR16C Programmer's reference manual. Part number: 424521772-101, National Semiconductor Inc.Google Scholar
- Shanon, C.E. 1948. A mathematical theory of communication. Bell Syst. Tech. J. 27, 398--403.Google Scholar
Cross Ref
- Van Dewiel, R. 2001. The code compaction bibliography. http://www.extra.research.philips.com/ccb/.Google Scholar
- Wolfe, A. and Chanin, A. 1992. Executing compressed programs on an embedded RISC architecture. In Proceedings of the 25th International Symposium on Microarchitecture (Micro). IEEE Computer Society Press, Los Alamitos, CA. 81--91. Google Scholar
Digital Library
- Xie, Y., Wolf, W. and Lekatsas, H. 2003. Profile-driven selective code compression. In Proceedings of the Conference on Design Automation and Test in Europe (DATE). IEEE Computer Society Press, Los Alamitos, CA. 462--467. Google Scholar
Digital Library
- Xie, Y., Wolf, W. and Lekatsas, H. 2006. Code compression for VLIW processors using variable-to-fixed coding. IEEE Trans. VLSI Syst. 14, 5, 525--536. Google Scholar
Digital Library
Index Terms
Code compression for performance enhancement of variable-length embedded processors
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