Abstract
Increasing demand for power-efficient, high-performance computing requires tuning applications and/or the underlying hardware to improve the mapping between workload heterogeneity and computational resources. To assess the potential benefits of hardware tuning, we propose a framework that leverages synergistic interactions between recent advances in (a) sampling, (b) predictive modeling, and (c) optimization heuristics. This framework enables qualitatively new capabilities in analyzing the performance and power characteristics of adaptive microarchitectures. For the first time, we are able to simultaneously consider high temporal and comprehensive spatial adaptivity. In particular, we optimize efficiency for many, short adaptive intervals and identify the best configuration of 15 parameters, which define a space of 240B point.
With frequent sub-application reconfiguration and a fully reconfigurable hardware substrate, adaptive microarchitectures achieve bips3/w efficiency gains of up to 5.3x (median 2.4x) relative to their static counterparts already optimized for a given application. This 5.3x efficiency gain is derived from a 1.6x performance gain and 0.8x power reduction. Although several applications achieve a significant fraction of their potential efficiency with as few as three adaptive parameters, the three most significant parameters differ across applications. These differences motivate a hardware substrate capable of comprehensive adaptivity to meet these diverse application requirements.
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- D. Albonesi. Dynamic IPC/clock rate optimization. In International Symposium on Computer Architecture, June 1998. Google Scholar
Digital Library
- D. Albonesi, R. Balasubramonian, S. Dropsho, S. Dwarkadas, E. Friedman, M. Huang, V. Kursun, G. Magklis, M. Scott, G. Semezaro, P. Bose, A. Buyuktosunoglu, P. Cook, and S. Schuster. Dynamically tuning processor resources with adaptive processing. IEEE Computer, December 2003. Google Scholar
Digital Library
- D. Bader, Y. Li, T. Li, and V. Sachdeva. Bioperf: A benchmark suite to evaluate high-performance computer architecture on bioinformatics applications. In IEEE International Symposium on Workload Characterization, October 2005.Google Scholar
Cross Ref
- R. Balasubramonian, D. Albonesi, A. Buyuktosunoglu, and S. Dwarkadas. Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures. In International Symposium on Microarchitecture, December 2000. Google Scholar
Digital Library
- D. Brooks, P. Bose, V. Srinivasan, M. Gschwind, P.G. Emma, and M.G. Rosenfield. New methodology for early-stage, microarchitecture-level power-performance analysis of microprocessors. IBM Journal of Research and Development, 47(5/6), Oct/Nov 2003. Google Scholar
Digital Library
- D. Brooks and et. al. Power-aware microarchitecture: Design and modeling challenges for next-generation microprocessors. IEEE Micro, 20(6):26--44, Nov/Dec 2000. Google Scholar
Digital Library
- A. Dhodapkar and J. Smith. Managing multi-configuration hardware via dynamic working set analysis. In International Symposium on Computer Architecture, June 2002. Google Scholar
Digital Library
- A. Efthymiou and J. Garside. Adaptive pipeline structures for speculation control. In International Symposium on Asynchronous Circuits and Systems, May 2003. Google Scholar
Digital Library
- E. Ipek, S.A. McKee, B. de Supinski, M. Schulz, and R. Caruana. Efficiently exploring architectural design spaces via predictive modeling. In Architectural support for programming languages and operating systems, October 2006. Google Scholar
Digital Library
- S. Eyerman, L. Eeckhout, and K.D. Bosschere. Efficient design space exploration of high performance embedded out-of-order processors. In Design, Automation, and Test in Europe, March 2006. Google Scholar
Digital Library
- D. Folegnani and A. Gonzalez. Energy-effective issue logic. In International Symposium on Computer Architecture, June 2001. Google Scholar
Digital Library
- G. Givens and J. Hoeting. Computational Statistics. Wiley, 2005.Google Scholar
- S. Gochman, R. Ronen, and et al. The intel pentium m processor: Micorarchitecture and performance. Intel Technology Journal, 7(2), May 2003.Google Scholar
- F. Harrell. Regression modeling strategies. Springer, 2001. Google Scholar
Digital Library
- J. Henning. Spec cpu2000: Measuring cpu performance in the new millenium. IEEE Computer, July 2000. Google Scholar
Digital Library
- M. Huang, J. Renau, and J. Torrellas. Positional adaptation of processors: Application to energy reduction. In International Symposium on Computer Architecture, June 2003. Google Scholar
Digital Library
- C. Hughes, J. Srinivasan, and S. Adve. Saving energy with architectural and frequency adaptations for multimedia applications. In International Symposium on Microarchitecture, December 2001. Google Scholar
Digital Library
- E. Ipek, M. Kirman, N. Kirman, and J. Martinez. Core fusion: Accommodating software diversity in chip multiprocessors. In International Symposium on Computer Architecture, June 2007. Google Scholar
Digital Library
- V. Iyengar, L. Trevillyan, and P. Bose. Representative traces for processor models with infinite cache. In International Symposium on High Performance Computer Architecture, February 1996. Google Scholar
Digital Library
- P. Joseph, K. Vaswani, and M.J. Thazhuthaveetil. A predictive performance model for superscalar processors. In International Symposium on Microarchitecture, December 2006. Google Scholar
Digital Library
- B. Lee and D. Brooks. Accurate and efficient regression modeling for microarchitectural performance and power prediction. In International Conference on Architectural Support for Programming Languages and Operating Systems, October 2006. Google Scholar
Digital Library
- B. Lee and D. Brooks. Illustrative design space studies with microarchitectural regression models. In International Symposium on High-Performance Computer Architecture, February 2007. Google Scholar
Digital Library
- X. Liang and D. Brooks. Mitigating the impact of process variations on cpu register file and execution units. In International Symposium on Microarchitecture, December 2006. Google Scholar
Digital Library
- K. Mai, T. Paaske, N. Jayasena, R. Ho, W. Dally, and M. Horowitz. Smart memories: A modular reconfigurable architecture. In International Symposium on Computer Architecture, June 2000. Google Scholar
Digital Library
- M. Moudgill, J. Wellman, and J. Moreno. Environment for PowerPC microarchitecture exploration. IEEE Micro, 19(3):9--14, May/June 1999. Google Scholar
Digital Library
- A. Phansalkar, A. Joshi, L. Eeckhout, and L. John. Measuring program similarity: experiments with SPEC CPU benchmark suites. In International Symposium on Performance Analysis of Systems and Software, March 2005. Google Scholar
Digital Library
- D. Ponomarev, G. Kucuk, and K. Ghose. Reducing power requirements of instruction scheduling through dynamic allocation of multiple datapath resources. In International Symposium on Microarchitecture, December 2001. Google Scholar
Digital Library
- R Development Team. R Language Definition.Google Scholar
- T. Sherwood, E. Perelman, G. Hamerly, and B. Calder. Automatically characterizing large scale program behavior. In International Conference on Architectural Support for Programming Languages and Operating Systems, October 2002. Google Scholar
Digital Library
- P. Shivakumar and N. Jouppi. An integrated cache timing, power, and area model. In Technical Report 2001/2, Compaq Computer Corporation, August 2001.Google Scholar
- A. Tiwari, S. Sarangi, and J. Torrellas. ReCycle: Pipeline adaptation to tolerate process variation. In International Symposium on Computer Architecture, June 2007. Google Scholar
Digital Library
- S. Woo, M. Ohara, E. Torrie, J. Singh, and A. Gupta. The SPLASH-2 programs: Characterization and methodological considerations. In International Symposium on Computer Architecture, June 1995. Google Scholar
Digital Library
- R.E. Wunderlich, T.F. Wenisch, B. Falsafi, and J.C. Hoe. SMARTS: Accelerating microarchitecture simulation via rigorous statistical sampling. In International Symposium on Computer Architecture, June 2003. Google Scholar
Digital Library
- V. Zyuban. Inherently lower-power high-performance superscalar architectures. In Ph.D. Thesis, University of Notre Dame, March 2000. Google Scholar
Digital Library
- V. Zyuban, D. Brooks, V. Srinivasan, M. Gschwind, P. Bose, P. Strenski, and P. Emma. Integrated analysis of power and performance for pipelined microprocessors. IEEE Transactions on Computers, Aug 2004. Google Scholar
Digital Library
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Efficiency trends and limits from comprehensive microarchitectural adaptivity
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