Andrea Calimera
R. Iris Bahar
ABSTRACT
Temperature fluctuations can alter the delay in MOS circuits. However, increases in temperature do not always lead to a corresponding increase in circuit delay, specifically when operating at low supply voltages. Instead a temperature inversion effect can be observed on the delay of MOS devices under certain conditions, where the delay actually decreases as temperature increases. Given these non-monotonic effects, guaranteeing timing correctness can no longer be achieved simply by characterizing the design under worst case (i.e., high temperature) conditions. In this paper, we present a synthesis methodology in which multi-Vth design is used to generate temperature-insensitive circuits, while minimizing leakage power dissipation as a side-effect. Our experiments with ISCAS benchmark circuits demonstrate the promise of this approach and show that significant reduction in static power is also possible.
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Index Terms
Temperature-insensitive synthesis using multi-vt libraries
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Reviews
Xiaojun Li
Technology advancement in nanometer very large-scale integration (VLSI) design demands smarter synthesis algorithms to automatically generate circuits with high speed and low power. Multiple-threshold voltage (Vt) devices are being employed more and more in state-of-the-art designs, because of the advantages resulting from the blending of high Vt devices (for low leakage) and low Vt devices (for high speed). However, these circuits are not immune to temperature effects, so their delay targets at both room and high temperatures may not be easily guaranteed at the same time. This paper introduces some new ideas to resolve this issue. The authors propose some advanced tweaks in multivoltage synthesis technology to guarantee delay targets at both low and high temperatures, while keeping overall power consumption low. The paper has a very nice technical review of the temperature behaviors of multiple Vt circuits, and analytically explains the different contributions from the two major parameters that drift with temperature: mobility and threshold voltage. The net results of these two parameters lead to different temperature behaviors for high-Vt and low-Vt devices. Based on these experimental observations, the authors propose a new synthesis algorithm that includes a new scale factor to guarantee delay targets at both ends of the product usage temperature range, and a replacing process to identify and replace noncritical low-Vt devices with high-Vt devices for leakage reduction. The experimental results show clear benefits for various standard circuits when using this new synthesis algorithm: all the tested circuits showed no delay violations at both room and high temperatures, and the overall power was reduced by an average of 38 percent. The theoretical part of the paper is well written; there is one weakness, however, in the experimental part presented in Section 4. In Table 1, only the high-temperature power dissipations were presented. Actually, it is important to also show the room temperature results, because at low temperatures, power improvements from high-Vt devices may be less when compared with those at high temperature. In general, the new synthesis algorithm suggests more low-Vt devices than obtained from the normal algorithm. Low-Vt devices result in low delay, and this is why the delay targets are guaranteed at both low and high temperatures. However, the dynamic power and static leakage are higher for low-Vt devices, and their tendency with temperature is unknown from the paper. As a result, at room temperature, the reduction of the total power from dynamic and static operations may not be as significant as those from high temperature. If this is true, then new effort needs to be taken by the authors to fine tune the algorithm to compensate for the increased device number, which may increase the design size to an unacceptable level. Online Computing Reviews Service
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