Jayanthi Ravindra
ABSTRACT
We present an algorithm for reducing large VLSI circuits to much smaller ones with similar input-output behavior. A key feature of our method, called generic subspace, is that it is capable of reducing linear time-varying systems. This enables it to capture frequency-translation and sampling behavior, important in communication subsystems such as mixers, RF components and switched-capacitor filters. Reduction is obtained by projecting the original system described by linear differential equations into subspace of a lower dimension. Experiments have been carried out using Cadence Design Simulator which indicates that the proposed sub-space technique achieves more % reduction with less CPU time than the other model order reduction techniques existing in literature. We also present applications to RF circuit subsystems, obtaining size reductions and evaluation speedups of orders of magnitude with insignificant loss of accuracy.
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Index Terms
Generic sub-space algorithm for generating reduced order models of linear time varying vlsi circuits
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