A low-power 12-bit 80MHz CMOS DAC using pseudo-segmentation

ABSTRACT

This paper describes the design of a low-power 12-bit CMOS DAC using pseudo-segmentation technique. Pseudo-segmentation used in binary decoder consists of simple parallel buffers for low power because of simpler configuration than that of thermometer decoder. The measurement results show the conversion rate of 80MHz and the power dissipation of 46.8mW at single supply voltage of 1.8V. ±1.6LSB / ±1.2LSB of INL and DNL have been measured for linearity. The ENOB and SFDR of the proposed 12bit DAC were measured to be 10.67 bit and 66.01dBc @ Fs=80MHz, Fin=1MHz, respectively. Glitch energy was measured to be 49 pV"s.

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Index Terms

• Hardware

  • Very large scale integration design