A linear programming formulation for security-aware gate sizing

ABSTRACT

Differential power analysis (DPA) has been shown to be the dominant type of side-channel attacks that significantly jeopardize the security in integrated circuits. It has been shown that the data, the functional unit operations as well as the internal micro-architectures can be detected through current and power analysis. Subsequently, different CMOS logic styles have been proposed in the literature for performing computations in such a manner that the current and power signatures can be concealed through reduction of the variance in transient power dissipation. In this work, we propose a gate sizing formulation based on traditional static CMOS standard cells that improves the security of the circuits while maintaining low overheads in terms of area, power and delay. The proposed algorithm considers all disjoint paths from primary inputs to the primary outputs, performing gate sizing with the objective of balancing the switched path capacitances among the various paths making it difficult to extract power or current signatures through current or power profiling. Further, we show that the path based security aware gate sizing formulation is NP-complete and propose a greedy approximation algorithm based on linear programming. The proposed algorithm has been implemented and validated on the ISCAS85 benchmarks and the experimental results indicate a reduction of the variance of transient dynamic power by about 40% with very low overhead in terms of delay, area and power.

References

1. M. Berkelaar and J. Jess. Gate sizing in mos digital circuits with linear programming. Proc. of EDAC, pages 217--221, 1990.
2. J. Fishburn and A. Dunlop. Tilos: A posynomial programming approach to transistor sizing. Proc. of ICCAD, pages 326--328, 1985.
3. N. Hanchate and N. Ranganathan. Simultaneous interconnect delay and crosstalk noise optimization through gate sizing using game theory. Trans. on Computers, 55(8):1011--1023, 2006.
4. P. Kocher, J. Jaffe, and B. Jun. Differential power analysis. Proc. of Intl. Cryptology Conf. on Advances in Cryptology, pages 388--397, 1999.
5. O. Kommerling and M. Kuhn. Design principles for tamper-resistant smartcard processors. Workshop on Smartcard Technology, pages 9--20, 1999.
6. V. Mahalingam, N. Ranganathan, and J. Harlow III. A novel approach for variation aware power minimization during gate sizing. Proc. of ISLPED, pages 174--179, 2006.
7. M. Mani and M. Orshansky. A new statistical optimization algorithm for gate sizing. Proc. of ICCD, pages 272--277, 2004.
8. A. Murugavel and N. Ranganathan. Gate sizing and buffer insertion using economic models for power optimization. Proc. of Intl. Conf. on VLSI Design, pages 195--200, 2004.
9. S. Ravi, A. Raghunathan, P. Kocher, and S. Hattangady. Security in embedded systems: Design challenges. Trans. on Embedded Computing Systems, pages 361--391, 2004.
10. S. Sapatnekar, V. Rao, and P. Vaidya. An exact solution to the transistor sizing problem for cmos circuits using convex optimization. Trans. on CAD, 12(11):1621--1634, 1993.
11. J. Singh, V. Nookala, Z. Luo, and S. Sapatnekar. Robust gate sizing by geometric programming. Proc. of DAC, pages 315--320, 2005.
12. D. Sinha and H. Zhou. Gate sizing for crosstalk reduction under timing constraints by lagrangian relaxation. Proc. of ICCAD, pages 14--19, 2004.
13. K. Tiri and I. Verbauwhede. A dynamic and differential cmos logic with signal independent power consumption to withstand differential power analysis on smart cards. Proc. of Conf. of Solid--State Circuits, 2002.
14. K. Tiri and I. Verbauwhede. A logic level design methology for a secure dpa resistant asic or fpga implementation. Proc. of DATE, pages 246--251, 2004.
15. K. Tiri and I. Verbauwhede. A digital design flow for secure integrated circuits. Trans. on CAD, 25(7):1197--1208, 2006.
16. X. Yang and K. Saluja. Combating nbti degradation via gate sizing. Proc. of ISQED, pages 47--52, 2007.
17. Q. Zhou and K. Mohanram. Gate sizing to radiation harden combinational logic. Trans. on CAD, 25(1):155--166, 2006.

Index Terms

• Applied computing

  • Arts and humanities

    • Architecture (buildings)

      • Computer-aided design

  • Physical sciences and engineering

    • Engineering

      • Computer-aided design

• Hardware

  • Electronic design automation

    • High-level and register-transfer level synthesis