On efficient generation of instruction sequences to test for delay defects in a processor

ABSTRACT

We present a technique that deals with the problem of efficiently generating instruction sequences to test for delay defects in a processor. These instruction sequences are loaded into the cache of a processor and the processor is run in its normal functional (native) mode to test itself. The methodology that we present avoids the significant increase in search space of a previous method while generating tests. We also present a technique which increases the probability of detecting multiple delay faults with a single instruction sequence. This technique can help immensely in reducing the cost of test. We demonstrate the effectiveness of our technique on an off-the shelf processor.

References

1. P. Gelsinger, "Discontinuities driven by a billion connected machines," IEEE Design and Test of Computers, vol. 17, no. 1, pp. 7--15, 2000.
2. S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, and V. De,"Parameter variations and impact on circuits and microarchitecture," in Proceedings of the 40th conference on Design automation, 2003, pp.338--342.
3. W.--C. Lai, A. Krstic, and K.--T. Cheng, "On testing the path delay faults of a microprocessor using its instruction set," in VTS '00: Proceedings of the 18th IEEE VLSI Test Symposium (VTS'00), 2000, p. 15.
4. J. Shen and J. A. Abraham, "Native mode functional test generation for processors with applications to self test and design validation," in Proceedings of the International Test Conference, Oct 1998, pp.990--999.
5. P. Parvathala, K. Maneparambil, and W. Lindsay, "FRITS -- a microprocessor functional BIST method," in Proceedings of the International Test Conference, Oct 2002, pp. 590--598.
6. S. Gurumurthy, S. Vasudevan, and J. A. Abraham, "Automated mapping of precomputed module--level test sequences to processor instructions," in Proceedings of the International Test Conference, Nov 2005, p. 12.3.
7. S. Gurumurthy, S. Vasudevan, and J. A. Abraham, "Automatic generation of instruction sequences targeting hard--to--detect structural faults in a processor," in Proceedings of the International Test Conference, Oct 2006, p. 27.3.
8. N. Kranitis, A. Paschalis, D. Gizopoulos, and Y. Zorian, "Effective software self--test methodology for processor cores," in Proceedings of the conference on Design, automation and test in Europe, 2002, pp. 592--597.
9. F. Corno, G. Cumani, M. S. Reorda, and G. Squillero, "Fully automatic test program generation for microprocessor cores," in Proceedings of the conference on Design, Automation and Test in Europe, 2003, pp. 1006-- 1011.
10. W.--C. Lai, A. Krstic, and K.-T. Cheng, "Test program synthesis for path delay faults in microprocessor cores," in Proceedings of the International Test Conference, 2000, p. 1080.
11. V. Singh, M. Inoue, K. K. Saluja, and H. Fujiwara, "Instruction--based delay fault self--testing of pipelined processor cores," in IEEE International Symposium on Circuits and Systems, 2005, pp. 5686--5689.
12. S. Gurumurthy, R. Vemu, J. A. Abraham, and D. G. Saab, "Automatic generation of instructions to robustly test delay defects in processors," in Proceedings of the European Test Symposium, May 2007, pp. 173--178.
13. K. J. Balakrishnan, N. A. Touba, and S. Patil, "Compressing functional tests for microprocessors," in Proceedings of the Asian Test Symposium, 2005, pp. 428--433.
14. "BMC engine of Symbolic Model Verifier," http://www--cad.eecs.berkeley.edu/~kenmcmil/smv/.
15. A. Virazel, R. David, P. Girard, C. Landrault, and S. Pravossoudovitch, "Delay fault testing: Choosing between random sic and random mic test sequences," Journal of Electronic Testing: Theory and Applications, vol. 17, no.3--4, pp. 233--241, 2001.
16. P. Bernardi, M. Grosso, and M. S. Reorda, "Hardware--accelerated path--delay fault grading of functional test programs for processor--based systems," in Proceedings of the Great lakes symposium on VLSI, 2007, pp. 411--416.
17. R. Jayabharathi, "Hierarchical timing verification and delay fault testing," PhD Dissertation, The University of Texas, Aug. 1999.
18. "OR1200 RISC processor," http://www.opencores.org.

Index Terms

• Hardware

  • Hardware test

  • Robustness