Richard Putman
ABSTRACT
This paper addresses the problem of increasing unknowns in the output response data by exploring reiterative LFSR reseeding based X-masking. This approach takes advantage of the data correlation in the output response data to enable LFSR encoded masks to be reused for multiple scan slices while guaranteeing that all unknowns are masked and all bits required for fault detection are allowed to propagate to the compactor. This paper also investigates a hybrid approach that combines conventional LFSR reseeding based X-masking with fixed-interval reiterative LFSR X-masking. Experimental results for applying this approach to industrial designs indicate that significant amounts of output compression can be achieved without any pattern count inflation or loss in fault coverage.
- Touba, N.A., "Survey of Test Vector Compression Techniques," IEEE Design & Test, Vol. 23, Issue 4, pp. 294-303, Jul. 2006. Google Scholar
Digital Library
- Wang, L.T., C.-W. Wu, X. Wen, VLSI Test Principles and Architectures, Morgan Kaufmann, 2006. Google ScholarDigital Library
- Barnhart, C., V. Brunkhorst, F. Distler, O. Farnsworth, B. Keller, and B. Koenemann, "OPMISR: the Foundation for Compressed ATPG Vectors," Proc. of International Test Conference , pp. 748-757, 2001. Google ScholarDigital Library
- Wohl, P., J.A. Waicukauski, S. Patel, and M.B. Amin, "X-Tolerant Compression and Application of Scan-ATPG Patterns in a BIST Architecture," Proc. of International Test Conference, pp. 727-736, 2003.Google Scholar
- Wohl, P., J.A. Waicukauski, and S. Patel, "Scalable Selector Architecture for X-Tolerant Deterministic BIST," Proc. of Design Automation Conference, pp. 934-939, 2004. Google ScholarDigital Library
- Pomeranz, I., S. Kundu, and S.M. Reddy, "On Output Response Compression in the Presense of Unknown Output Values," Proc. of Design Automation Conference, pp. 255-258, 2002. Google ScholarDigital Library
- Chickermane, V., B. Foutz, and B. Keller, "Channel Masking Synthesis for Efficient On-Chip Test Compression," Proc. of International Test Conference, pp. 452-461, 2004. Google ScholarDigital Library
- Naruse, M., I. Pomeranz, S.M. Reddy, and S. Kundu, "On-Chip Compression of Output Responses with Unknown Values Using LFSR Reseeding," Proc. of International Test Conference, pp. 1060-1068, 2003.Google Scholar
- Volkerink, E.H., and S. Mitra, "Response Compaction with Any Number of Unknowns Using a New LFSR Architecture," Proc. of Design Automation Conference, pp. 117-122, 2005. Google ScholarDigital Library
- Chao, M. C.-T., S. Wang, S.T. Chakradhar, and K.-T. Cheng, "Response Shaper: A Novel Technique to Enhance Unknown Tolerance for Output Response Compaction," Proc. of International Conference on Computer-Aided Design, pp. 80-87, 2005. Google ScholarDigital Library
- Mitra, S., and K.S. Kim, "X-Compact: An Efficient Response Compaction Scheme," IEEE Trans. on Computer-Aided Design, Vol. 23, No. 3, pp. 421-432, Mar. 2004. Google ScholarDigital Library
- Rajski, J., J. Tyszer, C. Wang, and S.M. Reddy, "Finite Memory Test Response Compactors for Embedded Test Applications," IEEE Trans. on Computer-Aided Design, Vol. 24, No. 4, pp. 622-634, Apr. 2005. Google ScholarDigital Library
- Touba, N.A., "X-Canceling MISR -- An X-Tolerant Methodology for Compacting Output Responses with Unknowns Using a MISR," Proc. of International Test Conference, Paper 6.2, 2007.Google Scholar
Index Terms
Using reiterative LFSR based X-masking to increase output compression in presence of unknowns
Recommendations
Interval Based X-Masking for Scan Compression Architectures
ISQED '08: Proceedings of the 9th international symposium on Quality Electronic DesignTest stimulus and response compaction (Scan Compression) in scan is increasingly becoming an integral part of today’s design-for-test (DFT) methodology for achieving high quality test at lower costs. Current generation integrated circuit’s (ICs) are ...
Masking of X-values by Use of a Hierarchically Configurable Register
ETS '09: Proceedings of the 2009 European Test SymposiumIn this paper we consider the test of large circuits. Due to the increasing number of scan chains of industrial designs and due to the limited recourses of the ATE-equipment the compression ratio of the test responses increases. A second issue are ...
Using partial masking in X-chains to increase output compaction for an X-canceling MISR
DFT '12: Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)An X-Canceling MISR [Touba 07] provides the ability to tolerate unknowns (X's) in the output response with very little loss of observability of non-X values. When the density of X's is low, an X-Canceling MISR is extremely efficient as the number of ...
Comments