skip to main content
research-article

Parametric Yield Modeling and Simulations of FPGA Circuits Considering Within-Die Delay Variations

Published:01 June 2008Publication History
Skip Abstract Section

Abstract

Variations in the semiconductor fabrication process results in differences in parameters between transistors on the same die, a problem exacerbated by lithographic scaling. Field-Programmable Gate Arrays may be able to compensate for within-die delay variability, by judicious use of reconfigurability. This article presents two strategies for compensating within-die stochastic delay variability by using reconfiguration: reconfiguring the entire FPGA, and relocating subcircuits within an FPGA. Analytical models for the theoretical bounds on the achievable gains are derived for both strategies and compared to models for worst-case design as well as statistical static timing analysis (SSTA). All models are validated by comparison to circuit-level Monte Carlo simulations. It is demonstrated that significant improvements in circuit yield and timing are possible using SSTA alone, and these improvements can be enhanced by employing reconfiguration-based techniques.

References

  1. Abramovici, M. and Stroud, C. E. 2003. BIST-based delay-fault testing in FPGAs. J. Electr. Test.: Theory Appl. 19, 5, 549--558. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. Asenov, A., Kaya, S., and Brown, A. R. 2003. Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness. IEEE Trans. Electr. Devices 50, 5, 1254--1260.Google ScholarGoogle ScholarCross RefCross Ref
  3. Asenov, A., Kaya, S., and Davies, J. H. 2002. Intrinsic threshold voltage fluctuationsin decananometer MOSFETs due to local oxide thickness variations. IEEE Trans. Electr. Devices 49, 6, 112--119.Google ScholarGoogle ScholarCross RefCross Ref
  4. Betz, V. and Rose, J. 1997. VPR: A new packing, placement and routing tool for FPGA research. In Proceedings of the Field-Programmable Logic and Applications. Springer. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. Cao, Y., Gupta, P., Kahng, A. B., Sylvester, D., and Yang, J. 2002. Design sensitivities to variability: Extrapolations and assessments in nanometer VLSI. In Proceedings of the IEEE International ASIC/SOC Conference.Google ScholarGoogle Scholar
  6. Cattell, R. B. 1966. The scree test for the number of factors. Multivariate Behav. Resear. 1, 245--276.Google ScholarGoogle ScholarCross RefCross Ref
  7. Chang, H., Zolotov, V., Narayan, S., and Visweswariah, C. 2005. Parameterized block-based statistical timing analysis with non-Gaussian parameters, nonlinear delay functions. In Proceedings of the Design Automation Conference. Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. Girard, P., Héron, O., Pravossoudovitch, S., and Renovell, M. 2004. High quality TPG for delay faults in look-up tables of FPGAs. In Proceedings of the IEEE International Workshop on Electronic Design, Test and Applications. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. Harris, I. G., Menon, P. R., and Tessier, R. 2001. BIST-based delay path testing in FPGA architectures. In Proceedings of the IEEE International Test Conference. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. Katsuki, K., Kotani, M., Kobayashi, K., and Onodera, H. 2005. A yield and speed enhancement scheme under within-die variations on 90nm LUT array. In Proceedings of the IEEE Custom Integrated Circuits Conference.Google ScholarGoogle Scholar
  11. Katsuki, K., Kotani, M., Kobayashi, K., and Onodera, H. 2006. Measurement results of within-die variations on a 90nm LUT array for speed and yield enhancement of reconfigurable devices. In Proceedings of the Asia and South Pacific Design Automation Conference. Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. Kim, K. S., Mitra, S., and Ryan, P. G. 2003. Delay defect characteristics and testing strategies. IEEE Design Test Comput. 20, 5, 8--16. Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. Kraśniewski, A. 2003. Evaluation of testability of path delay faults for user-configured programmable devices. In Proceedings of the Field-Programmable Logic and Applications. IEEE.Google ScholarGoogle ScholarCross RefCross Ref
  14. Li, X.-Y., Wang, F., La, T., and Ling, Z.-M. 2004. FPGA as process monitor--an effective method to characterize poly gate CD variation and its impact on product performance and yield. IEEE Trans. Semicond. Manuf. 17, 3, 267--272.Google ScholarGoogle ScholarCross RefCross Ref
  15. Lin, Y., Hutton, M., and He, L. 2006. Placement and timing for FPGAs considering variations. In Proceedings of the Field-Programmable Logic and Applications. IEEE.Google ScholarGoogle Scholar
  16. Matsumoto, Y., Hioki, M., Kawanami, T., Tsutsumi, T., Nakagawa, T., Sekigawa, T., and Koike, H. 2007. Performance and yield enhancement of FPGAs with within-die variation using multiple configurations. In Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays. ACM. Google ScholarGoogle ScholarDigital LibraryDigital Library
  17. Nabaa, G., Azizi, N., and Najm, F. N. 2006. An adaptive FPGA architecture with process variation compensation and reduced leakage. In Proceedings of the Design Automation Conference. Google ScholarGoogle ScholarDigital LibraryDigital Library
  18. Nassif, S. R. 2000. Design for variability in DSM technologies. In Proceedings of the IEEE International Symposium on Quality Electronic Design. Google ScholarGoogle ScholarDigital LibraryDigital Library
  19. Sedcole, P., Blodget, B., Becker, T., Anderson, J., and Lysaght, P. 2006. Modular dynamic reconfiguration in Virtex FPGAs. IEE Proc. Comput. Digital Techniq. 153, 3, 157--164.Google ScholarGoogle ScholarCross RefCross Ref
  20. Sedcole, P. and Cheung, P. Y. K. 2006. Within-die delay variability in 90nm FPGAs and beyond. In Proceedings of the IEEE International Conference on Field Programmable Technology.Google ScholarGoogle Scholar
  21. Sedcole, P. and Cheung, P. Y. K. 2007. Parametric yield in FPGAs due to within-die delay variations: A quantitative analysis. In Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays. ACM. Google ScholarGoogle ScholarDigital LibraryDigital Library
  22. Visweswariah, C. 2003. Death, taxes and failing chips. In Proceedings of the Design Automation Conference. Google ScholarGoogle ScholarDigital LibraryDigital Library
  23. Visweswariah, C., Ravindran, K., Kalafala, K., Walker, S. G., and Narayan, S. 2004. First-order incremental block-based statistical timing analysis. In Proceedings of the Design Automation Conference. Google ScholarGoogle ScholarDigital LibraryDigital Library
  24. Wong, H.-Y., Cheng, L., Lin, Y., and He, L. 2005. FPGA device and architecture evaluation considering process variation. In Proceedings of the International Conference on Computer-Aided Design. Google ScholarGoogle ScholarDigital LibraryDigital Library
  25. Zhao, W., Liu, F., Agarwal, K., Acharyya, D., Nassif, S., Nowka, K., and Cao, Y. 2007. Rigorous extraction of process variations for 65nm CMOS design. In Proceedings of the European Solid-State Circuits Conference.Google ScholarGoogle Scholar

Index Terms

  1. Parametric Yield Modeling and Simulations of FPGA Circuits Considering Within-Die Delay Variations

      Recommendations

      Comments

      Login options

      Check if you have access through your login credentials or your institution to get full access on this article.

      Sign in

      Full Access

      PDF Format

      View or Download as a PDF file.

      PDF

      eReader

      View online with eReader.

      eReader
      About Cookies On This Site

      We use cookies to ensure that we give you the best experience on our website.

      Learn more

      Got it!