ABSTRACT
Instruction selection is a well-studied compiler phase that translates the compiler's intermediate representation of programs to a sequence of target-dependent machine instructions optimizing for various compiler objectives (e.g. speed and space). Most existing instruction selection techniques are limited to the scope of a single statement or a basic block and cannot cope with irregular instruction sets that are frequently found in embedded systems.
We consider an optimal technique for instruction selection that uses Static Single Assignment (SSA) graphs as an intermediate representation of programs and employs the Partitioned Boolean Quadratic Problem (PBQP) for finding an optimal instruction selection. While existing approaches are limited to instruction patterns that can be expressed in a simple tree structure, we consider complex patterns producing multiple results at the same time including pre/post increment addressing modes, div-mod instructions, and SIMD extensions frequently found in embedded systems. Although both instruction selection on SSA-graphs and PBQP are known to be NP-complete, the problem can be solved efficiently - even for very large instances.
Our approach has been implemented in LLVM for an embedded ARMv5 architecture. Extensive experiments show speedups of up to 57% on typical DSP kernels and up to 10% on SPECINT 2000 and MiBench benchmarks. All of the test programs could be compiled within less than half a minute using a heuristic PBQP solver that solves 99.83% of all instances optimally.
- Warren P. Adams and Richard J. Forrester. A simple recipe for concise mixed 0-1 linearizations. Oper. Res. Lett., 33(1):55--61, 2005. Google Scholar
Digital Library
- A. V. Aho and S. C. Johnson. Optimal code generation for expression trees. J. ACM, 23(3):488--501, 1976. Google Scholar
Digital Library
- A. Balachandran, D. M. Dhamdhere, and S. Biswas. Efficient retargetable code generation using bottom-up tree pattern matching. Computer Languages, 15(3):127--140, 1990. Google Scholar
Digital Library
- Ron Cytron, Jeanne Ferrante, Barry K. Rosen, Mark N. Wegman, and F. Kenneth Zadeck. Efficiently Computing Static Single Assignment Form and the Control Dependence Graph. ACM Transactions on Programming Languages and Systems, 13(4):451--490, October 1991. Google Scholar
Digital Library
- João Dias and Norman Ramsey. Converting intermediate code to assembly code using declarative machine descriptions. In Alan Mycroft and Andreas Zeller, editors, CC, volume 3923 of Lecture Notes in Computer Science, pages 217--231. Springer, 2006. Google Scholar
Digital Library
- Erik Eckstein. Code Optimization for Digital Signal Processors. PhD Thesis. TU Wien, November 2003.Google Scholar
- Erik Eckstein, Oliver König, and Bernhard Scholz. Code Instruction Selection Based on SSA-Graphs. In Andreas Krall, editor, SCOPES, volume 2826 of Lecture Notes in Computer Science, pages 49--65. Springer, 2003.Google Scholar
- M. Anton Ertl. Optimal Code Selection in DAGs. In Principles of Programming Languages (POPL '99), 1999. Google Scholar
Digital Library
- M. Anton Ertl, Kevin Casey, and David Gregg. Fast and flexible instruction selection with on-demand tree-parsing automata. In PLDI '06: Proceedings of the 2006 ACM SIGPLAN conference on Programming language design and implementation, pages 52--60, New York, NY, USA, 2006. ACM Press. Google Scholar
Digital Library
- Robert W. Floyd. Algorithm 97: Shortest path. Commun. ACM, 5(6):345, 1962. Google Scholar
Digital Library
- C. Fraser, R. Henry, and T. Proebsting. BURG - Fast Optimal Instruction Selection and Tree Parsing. ACM SIGPLAN Notices, 27(4):68--76, April 1992. Google Scholar
Digital Library
- Christopher W. Fraser, David R. Hanson, and Todd A. Proebsting. Engineering a simple, efficient code-generator generator. ACM Letters on Programming Languages and Systems, 1(3):213--226, September 1992. Google Scholar
Digital Library
- Michael P. Gerlek, Eric Stoltz, and Michael Wolfe. Beyond Induction Variables: Detecting and Classifying Sequences Using a Demand-Driven SSA Form. ACM Transactions on Programming Languages and Systems, 17(1):85--122, 1995. Google Scholar
Digital Library
- J. Guo, T. Limberg, E. Matus, B. Mennenga, R. Klemm, and G. Fettweis. Code generation for STA architecture. In Proc. of the 12th European Conference on Parallel Computing (Euro-Par'06). Springer LNCS, 2006. Google Scholar
Digital Library
- Lang Hames and Bernhard Scholz. Nearly optimal register allocation with PBQP. In David E. Lightfoot and Clemens A. Szyperski, editors, JMLC, volume 4228 of Lecture Notes in Computer Science, pages 346--361. Springer, 2006. Google Scholar
Digital Library
- Hannes Jakschitsch. "Befehlsauswahl auf SSA-Graphen". Master's thesis, Fakultät für Informatik, Universität Karlsruhe (TH),Germany, 2004.Google Scholar
- SPEC2000 Website. http://www.spec.org.Google Scholar
- Chris Lattner and Vikram S. Adve. LLVM: A compilation framework for lifelong program analysis & transformation. In Code Generation and Optimization, CGO 2004, pages 75--88, Palo Alto, CA, March 2004. IEEE Computer Society. Google Scholar
Digital Library
- Rainer Leupers and Steven Bashford. Graph-based code selection techniques for embedded processors. ACM Transactions on Design Automation of Electronic Systems., 5(4):794--814, 2000. Google Scholar
Digital Library
- Stan Liao, Srinivas Devadas, Kurt Keutzer, and Steve Tjiang. Instruction selection using binate covering for code size optimization. In Proc. Int'l Conf. on Computer-Aided Design, pages 393--399, 1995. Google Scholar
Digital Library
- MiBench Website. http://www.eecs.umich.edu/mibench/.Google Scholar
- Albert Nymeyer and Joost-Pieter Katoen. Code generation based on formal BURS therory and heuristic search. Acta Inf., 34(8):597--635, 1997.Google Scholar
Cross Ref
- Todd A. Proebsting. Least-Cost Instruction Selection in DAGs is NP-Complete. http://research.microsoft.com/~toddpro/papers/proof.htm, 1998.Google Scholar
- Stefan Schäfer and Bernhard Scholz. Optimal chain rule placement for instruction selection based on SSA graphs. In SCOPES '07: Proceedingsof the 10th international workshop on Software & compilers for embedded systems, pages 91--100, Nice, France, 2007. ACM. Google Scholar
Digital Library
- Bernhard Scholz and Erik Eckstein. Register Allocation for Irregular Architectures. In LCTES-SCOPES '02: Proceedings of the Joint Conference on Languages, Compilers and Tools for Embedded Systems, pages 139--148, 2002. Google Scholar
Digital Library
- Vojin živojnovi#263;, Juan M. Velarde, Christian Schläger, and Heinrich Meyr. DSPSTONE: A DSP-oriented benchmarking methodology. In Proceedings of the International Conference on Signal Processing and Technology (ICSPAT'94), 1994.Google Scholar
Index Terms
Generalized instruction selection using SSA-graphs
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