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Modeling and analysis of core-centric network processors

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Published:01 August 2008Publication History
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Abstract

Network processors can be categorized into two types, the coprocessors-centric model in which data-plane is handled by coprocessors, and the core-centric model in which the core processes most of the data-plane packets yet offloading some tasks to coprocessors. While the former has been properly explored over various applications, research regarding the latter remain limited. Based on the previous experience of prototyping the virtual private network (VPN) over the IXP425 network processor, this work aims to derive design implications for the core-centric model performing computational intensive applications. From system and IC vendors' perspectives, the continuous-time Markov chain and Petri net simulations are adopted to explore this architecture. Analytical results prove to be quite inline with those of the simulation and implementation. With subsequent investigation, we find that appropriate process run lengths can improve the effective core utilization by 2.26 times, and by offloading the throughput boosts 7.5 times. The results also suggest single-process programming, since context-switch overhead impacts considerably on the performance.

References

  1. Braun, T., Günter, M., Kasumi, M., and Khalil, I. 1999. Virtual private network architecture. Technical rep. IAM-99-001, CATI.Google ScholarGoogle Scholar
  2. Clark, C. et al. 2004. A hardware platform for network intrusion detection and prevention. In Proceedings of the 3rd Workshop on Network Processors and Applications (NP3). Madrid, Spain.Google ScholarGoogle Scholar
  3. Comer, D. and Martynov, M. 2006. Building experimental virtual routers with network processors. In Proceedings of the 2nd International Conference on Testbeds and Research Infrastructures for the Development of Networks and Communities (TRIDENTCOM).Google ScholarGoogle Scholar
  4. Crowley, P. and Baer, J.-L. 2002. A modeling framework for network processor systems. In Proceedings of the Network Processor Workshop in Conjunction with 8th International Symposium on High Performance Computer Architecture (NP1).Google ScholarGoogle Scholar
  5. Davis, J. D., Fu, C., and Laudon, J. 2005. The RASE (rapid, accurate simulation environment) for Chip Multiprocessors. In Proceedings of the Workshop on Design, Architecture and Simulation of Chip Multiprocessors (dasCMP'05). Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. Intel IXP425 Network Processor. http://www.intel.com/design/network/products/npfamily/ixp425.htm.Google ScholarGoogle Scholar
  7. Intel IXP2400 Network Processor. http://www.intel.com/design/network/products/npfamily/ixp2400.htm.Google ScholarGoogle Scholar
  8. Lekkas, P. C. 2003. Network Processors: Architectures, Protocols and Platforms (Telecom Engineering). McGraw-Hill, New York. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. Lin, Y.-D., Lin, Y.-N., Yang, S.-C., and Lin, Y.-S. 2003. DiffServ edge routers over network processors: Implementation and evaluation. IEEE Netw. 17, 4, 28--34. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. Lin, Y.-N., Lin, C.-H., Lin, Y.-D., and Lai, Y.-C. 2005. VPN Gateways over network processors: Implementation and evaluation. In Proceedings of the 11th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'05). San Francisco, CA. Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. Lin, Y.-N., Chang, Y.-C., Lin, Y.-D., and Lai, Y.-C. Lai. 2007. Resource allocation in network processors for memory access intensive applications. J. Syst. Softw. 80, 7. Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. Lu, J. and Wang, J. 2006. Analytical performance analysis of network-processor-based application designs. In Proceedings of the 15th International Conference on Computer Communications and Networks (IC3N'06). IEEE Press, Los Alamitos, CA. 33--39.Google ScholarGoogle Scholar
  13. Microsoft TechNet. http://www.microsoft.com/technet/prodtechnol/windows2000serv/reskit/core/fned_ana_trrf.mspx?mfr=true.Google ScholarGoogle Scholar
  14. Murata, T. 1989. Petri Nets: Properties, analysis and applications. Proc. IEEE 77, 4.Google ScholarGoogle ScholarCross RefCross Ref
  15. Nussbaum, D., Fedorova, A., and Small, C. 2004. An Overview of the Sam CMT simulator kit. Technical rep., Sun Microsystems. Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. Ratzer, A.V. et al. 2003. CPN Tools for editing, simulating, and analysing Coloured Petri Nets. In Proceedings of the International Conference on Applications and Theory of Petri Nets. Google ScholarGoogle ScholarDigital LibraryDigital Library
  17. Smith, J. M. S. 1997. Application-Specific Integrated Circuits. Addison-Wesley, Reading, MA.Google ScholarGoogle Scholar
  18. Tan, Z., Lin, C., Yin, H., and Li, B. 2004. Optimization and benchmark of cryptographic algorithms on network processors. IEEE Micro 24, 5, 55--69. Google ScholarGoogle ScholarDigital LibraryDigital Library
  19. Wolf, T. and Franklin, M. K. 2006. Performance models for network processor design. IEEE Trans. Parall. Distrib. Syst. 17, 6, 548--561. Google ScholarGoogle ScholarDigital LibraryDigital Library
  20. Zuberek, W. M., Govindarajan, R., and Suciu, F. 1998. Timed colored Petri net models of distributed memory multithreaded multiprocessors. In Proceedings of the Workshop on Practical Use of Colored Petri Nets and Design/CPN.Google ScholarGoogle Scholar

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