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Register allocation by puzzle solving

Published:07 June 2008Publication History
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Abstract

We show that register allocation can be viewed as solving a collection of puzzles. We model the register file as a puzzle board and the program variables as puzzle pieces; pre-coloring and register aliasing fit in naturally. For architectures such as PowerPC, x86, and StrongARM, we can solve the puzzles in polynomial time, and we have augmented the puzzle solver with a simple heuristic for spilling. For SPEC CPU2000, the compilation time of our implementation is as fast as that of the extended version of linear scan used by LLVM, which is the JIT compiler in the openGL stack of Mac OS 10.5. Our implementation produces x86 code that is of similar quality to the code produced by the slower, state-of-the-art iterated register coalescing of George and Appel with the extensions proposed by Smith, Ramsey, and Holloway in 2004.

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    • Published in

      cover image ACM SIGPLAN Notices
      ACM SIGPLAN Notices  Volume 43, Issue 6
      PLDI '08
      June 2008
      382 pages
      ISSN:0362-1340
      EISSN:1558-1160
      DOI:10.1145/1379022
      Issue’s Table of Contents
      • cover image ACM Conferences
        PLDI '08: Proceedings of the 29th ACM SIGPLAN Conference on Programming Language Design and Implementation
        June 2008
        396 pages
        ISBN:9781595938602
        DOI:10.1145/1375581
        • General Chair:
        • Rajiv Gupta,
        • Program Chair:
        • Saman Amarasinghe

      Copyright © 2008 ACM

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      Association for Computing Machinery

      New York, NY, United States

      Publication History

      • Published: 7 June 2008

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