Abstract
This article presents the design of a generic HyperTransport (HT) core. HyperTransport is a packet-based interconnect technology for low-latency, high-bandwidth point-to-point connections. It is specially optimized to achieve a very low latency. The core has been verified in system using an FPGA. This exhaustive verification and the generic design allow the mapping to both ASICs and FPGAs. The implementation described in this work supports a 16-bit link width, as used by Opteron processors. On a Xilinx Virtex-4 FX60, the core supports a link frequency of 400 MHz DDR and offers a maximum bidirectional bandwidth of 3.2GB/s. The in-system verification has been performed using a custom FPGA board that has been plugged into a HyperTransport extension connector (HTX) of a standard Opteron-based motherboard. HTX slots in Opteron-based motherboards allow very high-bandwidth, low-latency communication, since the HTX device is directly connected to one of the HyperTransport links of the processor. Performance analysis shows a unidirectional payload bandwidth of 1.4GB/s and a read latency of 180 ns. The HT core in combination with the HTX board is an ideal base for prototyping systems and implementing FPGA coprocessors. The HT core is available as open source.
- Advanced Micro Devices. 2006. AMD BIOS and kernel developer's guide for the AMD Athlon 64 and AMD Opteron processors, 26094, rev 3.3.Google Scholar
- Bees, D. and Holden B. 2004. HyperTransport reduces delays in some applications. http://www.eetimes.com/showArticle.jhtml?articleID=26100714.Google Scholar
- Castonguay, A. and Savaria, Y. 2005. A hypertransport chip-to-chip interconnect tunnel developed using systemC. In Proceedings of the 16th International Workshop on Rapid System Prototyping, Montreal, Canada. IEEE Computer Society, Washington, DC, 264--266. Google Scholar
Digital Library
- CELOXICA Ltd. 2006. Celoxica RCHTX-XV4 datasheet, version 1.0.Google Scholar
- Dickman, L., Lindahl, G. Olson, D. Rubin, J., and Broughton, J. 2005. PathScale InfiniPath: A first look Proceedings of the 13th Symposium on High Performance Interconnects (HOTI). IEEE Computer Society, Washington, DC, 163--165. Google Scholar
Digital Library
- DRC Computer. 2007. DRC RPU100-L60 datasheet.Google Scholar
- Fröning, H., Nüssle, M., Slogsnat, D., Litz, H., and Brüning, U. 2006. The HTX-Board: A rapid prototyping station. In Proceedings of the 3rd Annual FPGA World Conference, Stockholm, Sweden.Google Scholar
- Hong, J., Nurvitadhi, E., and Lu, S.-L. L. 2006. Design, implementation, and verification of active cache emulator (ACE). In Proceedings of the 14th International Symposium on Field Programmable Gate Arrays (FPGA). Monterey, CA. ACM, New York, NY, 63--72. Google Scholar
Digital Library
- HP. 2008. QuickSpecs HP ProLiant DL145 Generation 3 (G3), Datasheet, Version 16. h18004.www1.hp/com/products/quickspecs/12622-na/12622-na.pdf.Google Scholar
- HyperTransport Center of Excellence. 2008. HyperTransport Center of Excellence homepage. http://www.ra.informatik.uni-mannheim.de/coeht/.Google Scholar
- HyperTransport Technology Consortium. 2008. HP constrium. http://www.hypertransport.org/.Google Scholar
- HyperTransport Technology Consortium. 2005. HyperTransport I/O link specification revision 2.00b. Document HTC20031217--0036-0009. http://www.hypertransport.org/.Google Scholar
- HyperTransport Technology Consortium. 2006. HyperTransport I/O link specification revision 3.00. Document HTC20051222-0046-0008. http://www.hypertransport.org/.Google Scholar
- HyperTransport Technology Consortium. 2004. HyperTransport EATX motherboard/daughter- card specification. Document HTC2004105-0040-0011. findarticles.com/P/articles/mi_m0EIN/is_2004_Nov_9/ai_n6337625.Google Scholar
- HyperTransport Technology Consortium. 2005. The Future of High Performance Computing: Direct Low Latency Peripheral-to-CPU Connections: http://www.hpcsystems.com/pdf/The%20Future%20of%20HPC%20-%20Direct%20Low%20Latench%20Peripheral%20to%20CPU%20Connectivity.pdfGoogle Scholar
- IBM. 2007. IBM system x3455, datasheet. ftp://ftp.software.ibm.com/common/ssi/pm/sp/n/xsd02289usen/xsD02289USEN.PDF.Google Scholar
- Kuon, I. and Rose, J. 2006. Measuring the gap between FPGAs and ASICs. In Proceedings of the 14th International Symposium on Field Programmable Gate Arrays (FPGA), Monterey, CA. ACM, New York, NY, 21--30. Google Scholar
Digital Library
- LinuxBIOS. 2008. Coreboot homepage. http://www.linuxbios.org.Google Scholar
- Nüssle, M., Fröning, H., Giese, A., Litz, H., Slogsnat, D., and Brüning, B. 2007. A hypertransport based low-latency reconfigurable testbed for message-passing developments, two. In Proceeddings of the Workshop Kommunikation in Clusterrechnern und Clusterverbundsystemen (KiCC), Chemnitz, Germany.Google Scholar
- Schlansker, M., Chitlur, N., Oertli, E., Stillwell, P. M., Rankin, L., Bradeord, D., Carter, R. J., Mudigonda, J., Binkert, N., and Jouppi, N. P. 2007. High-Performance ethernet-based communications for future multi-core processors. In Proceedings of the Conference on Supercomputing (SC), Reno, NV. ACM, New York, 1--12. Google Scholar
Digital Library
- Suh, T., Lee, H.-H. S., Lu, S.-L., and Shen, J. 2006. Initial observations of hardware/software co-simulation using FPGA in architecture research. In Proceedings of the 2nd Workshop on Architecture Research Using FPGA Platforms, Austin.Google Scholar
- Tanabe, N., Yamamoto, J., Nishi, H., Kudoh, T., Hamada, Y., Nakajo, H., and Amano, H. 2000. MEMOnet: Network interface plugged into a memory slot. In Proceedings of the IEEE International Conference on Cluster Computing, Chemnitz Germany, 17--26.Google Scholar
- XILINX Corporation. 2004. HyperTransport Lite interface for Virtex-II FPGAs. Application Note, Document 1-800-255-7778.Google Scholar
- XTREMEDATA Inc. 2008. XtremeData XD1000 product brief. http://www.xtremedatainc.com/index.php?option=com_content&view=article&vid=106<emid=60.Google Scholar
Index Terms
An open-source HyperTransport core
Recommendations
A versatile, low latency HyperTransport core
FPGA '07: Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arraysThis paper presents the design of a generic HyperTransport (HT) core. It is specially optimized to achieve a very low latency. The core has been verified in system using the rapid prototyping methodology with FPGAs. This exhaustive verification and the ...
An Enhanced HyperTransport Controller with Cache Coherence Support for Multiple-CMP
NAS '09: Proceedings of the 2009 IEEE International Conference on Networking, Architecture, and StorageHyperTransport link is a high performance IO interface for system connection. In this paper, the architecture of a HyperTransport interface is introduced.This HyperTransport interface realizes efficient HT-AXI bidirectional transformation, where AXI is ...
Design and implementation of a plesiochronous multi-core 4x4 network-on-chip FPGA platform with MPI HAL support
FPGAworld '09: Proceedings of the 6th FPGAworld ConferenceThe Multi-Core NoC is a 4 by 4 Mesh NoC targeted for Altera FPGAs. It implements a deflective routing policy and is used to connect sixteen NIOS II processors. Each NIOS II is connected to the NoC via an address-mapped Resource Network Interface.
The ...






Comments