The network architecture of the Connection Machine CM-5 (extended abstract)

ABSTRACT

No abstract available.

References

1. 1.IEEE Std i149.1-1990. IEEE standard test access port and boundary-scan architecture~ 1990.
2. 2.G. E. Blelloch. Vector Models for Data-Parallel Computing. The MIT Press, 1990.
3. 3.W. J. Dally. Wire-efficient VLSI multiprocessor communication networks, in Paul Losleben, editor, Proceedings of the 1987 Stanford Conference on Advanced Research in VLSI, pages 391-415, Cambridge, MAt 1987. The MIT Press.
4. 4.W. J. Dally and C. L. Seitz. Deadlock-free message routing in muItiprocesor interconnection networks. IEEE Transactions on Computers, C-36(5):547-553, May 1987.
5. 5.F. Darema-Rogers, D. A. George, V. A. Norton, and G. F. Pfister. A single-program-multiple-data computational model for EPEX/FORTRAN. Research Report RC 11552, Computer Sciences Department, IBM T. J. Watson Research Center, Yorktown Heights, NY, November 1986.
6. 6.M. Dubois and S. Thakkar, editors. Cache Architectures in Tightly Coupled Multiprocessors. IEEE Computer Society, June 1990. Special Issue of Computer, Volume 23, Number 6.
7. 7.A. Gottlieb, R. Grishman, C. P. Kruskal, K. P. McAuliffe, L. Rudolph, and M. Snir. The NYU ultracomputer -- designing a MIMD~ shared-memory parallel machine. IEEE Transactions on Computers, C- 32(2):175-159, February 1983.
8. 8.R. I. Greenberg and C. E. Leiserson. Randomized routing on fat-trees. Advances in Computing Research, 5:345-374, 1989.
9. 9.R. Gupta. The fuzzy barrier: A mechanism for high speed synchronization of processors, in Third International Conference on Architectural Support for Programming Languages and Operating Systems, pages 54- 63, Boston, Massachusetts, 1989.
10. 10.J. L. Hennessy and D. A. Patterson. Computer Architecture A Quantitative Approach. Morgan Kaufmann, 1990.
11. 11.W. D. Hillis and G. L. Steele, Jr. Data parallel algorithms. Communications of the ACM, 29(12):1170- i183~ December 1986.
12. 12.H. F. Jordan. A multi-microprocessor system for finite element structural analysis. In A. K. Noor and Jr. McComb, H. G., editors, Trends in Computerized Structural Analysis and Synthesis, pages 21-29. Pergamon Press Ltd, 1978. Published as a special issue of Computers ~J Structures, Volume 10, Numbers 1-2.
13. 13.P. Kermani and L. Kleinrock. Virtual cut-through: A new computer communication switching technique. Computer Networks~ 3:267-286, 1979.
14. 14.F. T. Leighton, B. Maggs~ and S. Rao. Universal packet routing algorithms. In 29th Annual IEEE Symposium on Foundations of Computer Science, pages 256-271, 1988.
15. 15.C. E. Leiserson. Fat-trees: Universal networks for hardware-efficient supercomputing. IEEE Transactions on Computers, C-34(10):892-901, October 1985.
16. 16.C. E. Leiserson and B. M. Maggs. Communicationefficient parallel algorithms for distributed randomaccess machines. Algorithmica, 3:53-77, 1988.
17. 17.M. St. Pierre, S.-W. Yang, and D. Cassiday. Functional VLSI design verification methodology for the CM-5 massively parallel supercomputer. In International Conference on Computer Design, October 1992. To appear.
18. 18.C. L. Seitz. The cosmic cube. Communications of the ACM, 28(1):22-23, January 1985.
19. 19.C. L. Seitz, W. C. Athas, W. J. Dally~ R. Faucette, A. J. Martin, S. Mattisson, C. S. Steele, and W.-K. Su. Message-Passing Concurrent Computers: Their Architecture and Programming. Addison-Wesley, Reading, MA, 1986.
20. 20.P. Tang and P.-C. Yew. Processor self-scheduling for multiple-nested parallel loops. In K. Hwang, S. M. Jacobs, and E. E. Swartzlander, editors, Proceedings of the 1986 International Conference on Parallel Processing, pages 528-535, August 1986.
21. 21.Texas Instruments. SN54A CT8997, SN74A CT8997 Scan Path Linker With 4-bit identification Bus, April 1990. Product Preview.
22. 22.Thinking Machines Corporation, applicant. W. Daniel Hillis, inventor. European Patent Application Serial Number 89 902 461.6~ priority date of February 2, 1988, entitled Method and Apparatus For Aligning The Operation Of A Plurality 0/Processors. Also International Application Number WO 89/07299 (Published under the Patent Cooperation Treaty), Publication Date 10 August 1989.
23. 23.Thinking Machines Corporation, 245 First Street, Cambridge, MA 02154-1264. The Connection Machine CM- 5 Technical Summary, October 1991.
24. 24.R. Zak and J. Hill. An IEEE 1149.1 compliant testability architecture with internal scan. In International Conference on Computer Design, October 1992. To appear.

Index Terms

• Computer systems organization

  • Architectures

    • Parallel architectures

      • Multicore architectures

• Networks

  • Network architectures