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Exploiting instruction-level parallelism with the conjugate register file scheme

Published:10 December 1992Publication History
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References

  1. 1 G. 3. Cha/tin, "Register Allocation and Spilling Via Graph Coloring," Proceedings of tAe SIGPLAN '8~ $Timposium on Compiler Construction, SIGPLAN Notices, Vol. 17, no. 6 (June 1982), pp. 98-105. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. 2 M. D. Smith, M. S. Lain, and M. A. Horowitz, "Boosting Beyond Static Scheduling in a Superscalar Processor," Proceedings of the 17th Annual International Symposium on Computer Architecittre (May 1990), pp. 344-354. Google ScholarGoogle ScholarDigital LibraryDigital Library

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  1. Exploiting instruction-level parallelism with the conjugate register file scheme

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                    cover image ACM SIGMICRO Newsletter
                    ACM SIGMICRO Newsletter  Volume 23, Issue 1-2
                    Dec. 1992
                    300 pages
                    ISSN:1050-916X
                    DOI:10.1145/144965
                    Issue’s Table of Contents
                    • cover image ACM Conferences
                      MICRO 25: Proceedings of the 25th annual international symposium on Microarchitecture
                      December 1992
                      301 pages
                      ISBN:0818631759

                    Copyright © 1992 Authors

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                    Association for Computing Machinery

                    New York, NY, United States

                    Publication History

                    • Published: 10 December 1992

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