
- 1 R.M. Keller, "Lookahead Processors," Computing Surveys, Vol. 7, No. 4, pp. 514-537, December 1973. Google Scholar
Digital Library
- 2 S. Vassiliadis, J. Phillips and B. B laner, "Interlock Collapsing ALUs," accepted for publication in IEEE Transactions on Computers. Google Scholar
Digital Library
- 3 D.W. Wall, "Limits of Instruction-Level Parallelism,'' Fourth International Symposium on Architectural Support for Programming Languages and Operating Systems, pp. 290-302, April 1991. Google Scholar
Digital Library
- 4 W. A. Wulf, "The WM Computer Architecture," Computer Architecture News, Vol. 16, No. 1, pp. 70-84, March 1988. Google Scholar
Digital Library
- 5 R.D. Acosta, J. Kjelstrup and H. Torng, "An Instruction Issuing Approach to Enhancing Performance in Multiple Functional Unit Processors," IEEE Transaction on Computers, Vol. 35, pp. 815-828, September 1986. Google Scholar
Digital Library
- 6 J.E. Smith and A. R. Pleszkun, "Implementing Precise Interrupts in Pipelined Processors," IEEE Transaction on Computers, Vol. 37, No. 5, pp. 562-573, May 1988. Google Scholar
Digital Library
- 7 S. Vassiliadis, B. Blaner and R. J. Eickemeyer, "SCISM: A Scalable Compound Instruction-Set Machine,'' submitted for publication, January 1992.Google Scholar
- 8 S. Vassiliadis, "Compound instruction-Set Machines,'' private communication, 1989.Google Scholar
- 9 S. Vassiliadis, B. Blaner and R. J. Eickemeyer, "On the Attributes of the SCISM Organization," Computer Architecture News, Vol. 20, No. 4, pp.44-53, September 1992. Google Scholar
Digital Library
- 10 J. Phillips and S. Vassiliadis, "High Performance 3-1 Interlock Collapsing ALUs," submitted for publication. Google Scholar
Digital Library
- 11 S. Vassiliadis and J. Phillips, Interlock Collapsing ALU Design, IBM Technical Report, Endicott, N.Y., TR 01.C115, p. 22., October 1991.Google Scholar
- 12 S. Vassiliadis, "Recursive Equation for Hardwired Binary Adders," International Journal of Electronics, Vol. 67, No. 2, pp. 201-213, August 1989.Google Scholar
Cross Ref
- 13 S. Vassiliadis, "A Comparison Between Adders With New Defined Carries and Traditional Schemes for Addition," International Journal of Electronics, Vol. 64, No. 4, pp. 617-626, August 1988.Google Scholar
Cross Ref
- 14 N. Malik, R. J. Eickemeyer and S. Vassiliadis, "Execution Interlock Collapsing Under Restricted Memory Models," to appear in Proceedings of the 7th international Symposium on Computer and Information Sciences, November 1992.Google Scholar
- 15 M. Butler, T. Yeh, Y. Patt, M. Alsup, H. Scales and M. Shebanow, "Single Instruction Stream Parallelism is Greater than Two," Proceedings, 18th Annual Symposium on Computer Architecture, pp. 276-286, May 1991. Google Scholar
Digital Library
- 16 N. Malik, R. J. Eickemeyer and S. Vassiliadis, "Instruction-Level Parallelism from Execution Interlock Collapsing," Computer Architecture News, Vol. 20, No. 4, pp. 38--43, September 1992. Google Scholar
Digital Library
- 17 N. Malik, R. J. Eickemeyer and S. Vassiliadis, "Architectural Effects on Dual Instruction Issue with Interlock Collapsing ALUs," to appear in Proceedings of the Twelfth Annual IEEE International Phoenix Conference on Computers and Communications, March 1993.Google Scholar
- 18 G. Kaine, MIPS R2000 RISC Architecture, Prentice Hall, Englewood Cliffs, NJ 07632, 1987.Google Scholar
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Interlock collapsing ALU for increased instruction-level parallelism
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Interlock collapsing ALU for increased instruction-level parallelism
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