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Tradeoffs in processor/memory interfaces for superscalar processors

Published:10 December 1992Publication History
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References

  1. 1 W. M. Johnson, Super-scalar processor design. PhD thesis, Department of Electrical Engineering, Stanford University, Stanford, California, June 1989. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. 2 D. Kroft, "Lockup-free instruction fetch/prefetch cache organization," in Proc. 8th Ann. Int'l. $ymp. Computer Architecture, pp. 81-87, May 1981. Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. 3 G.~ S. Sohi and M. Franklin, "High-bandwidth data memory systems for superscalar processors," in Proc. ~th Int'l. Conf. on Architectural Support for Prog. Lang. and Operating Systems., (Santa Clara, CA), pp. 53-62, Apr. 1991. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. 4 "Spec newsletter," Feb. 1989. SPEC, Fremont, CA.Google ScholarGoogle Scholar
  5. 5 T. M. Conte, Systematic computer architecture protoiyping. PhD thesis, Department of Electrical and Computer Engineering, University of Illinois, Urbana, Illinois, 1992. Google ScholarGoogle ScholarDigital LibraryDigital Library

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  1. Tradeoffs in processor/memory interfaces for superscalar processors

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            • Published in

              cover image ACM SIGMICRO Newsletter
              ACM SIGMICRO Newsletter  Volume 23, Issue 1-2
              Dec. 1992
              300 pages
              ISSN:1050-916X
              DOI:10.1145/144965
              Issue’s Table of Contents
              • cover image ACM Conferences
                MICRO 25: Proceedings of the 25th annual international symposium on Microarchitecture
                December 1992
                301 pages
                ISBN:0818631759

              Copyright © 1992 Author

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              Association for Computing Machinery

              New York, NY, United States

              Publication History

              • Published: 10 December 1992

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