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Translation hint buffers to reduce access time of physically-addressed instruction caches

Published:10 December 1992Publication History
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References

  1. 1 Bulent Abali. A Parallel Address Translation Mechanism For Microprocessors. Technical Report No. RC 13101, IBM Watson Research Center, September 1987.Google ScholarGoogle Scholar
  2. 2 Brian Bray and M. J. Flynn. Translation Hint Buffers To Reduce Access Time Of Physically-Addressed Instruction Caches. Technical Report No. CSL-TR-92-535, Computer Systems Laboratory, Stanford University, August 1992.Google ScholarGoogle ScholarCross RefCross Ref
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  9. 9 George Taylor, Peter Davies, and Michael Farmwald. The TLB Slice- A Low-Cost High Speed Address Translation Mechanism. In 17th International Symp. on Computer Arch., pages 355-363, May 1990. Google ScholarGoogle ScholarDigital LibraryDigital Library

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  1. Translation hint buffers to reduce access time of physically-addressed instruction caches

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