
- FaPa91 M. Farrens and A. Park, "Dynamic Base Register Caching: A Technique for Reducing Address Bus Width", Proceedings of the Eighteenth Annual International Symposium on Computer Architecture, Toronto, Canada (May 27-30, 1991), pp. 198-207. Google Scholar
Digital Library
- PaFa90 A. Park and M. Fattens, "Address Compression Through Base Register Caching", Proceedings of the 23rd Annual Symposium and Workshop on Microprogramming and Microarchitectures, Orlando, Florida (November 27-29, 1990), pp. 193-199. Google Scholar
Digital Library
Index Terms
Modifying VM hardware to reduce address pin requirements
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