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Synthesis and Optimization of 2D Filter Designs for Heterogeneous FPGAs

Published:01 January 2009Publication History
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Abstract

Many image processing applications require fast convolution of an image with one or more 2D filters. Field-Programmable Gate Arrays (FPGAs) are often used to achieve this goal due to their fine grain parallelism and reconfigurability. However, the heterogeneous nature of modern reconfigurable devices is not usually considered during design optimization. This article proposes an algorithm that explores the space of possible implementation architectures of 2D filters, targeting the minimization of the required area, by optimizing the usage of the different components in a heterogeneous device. This is achieved by exploring the heterogeneous nature of modern reconfigurable devices using a Singular Value Decomposition based algorithm, which provides an efficient mapping of filter's implementation requirements to the heterogeneous components of modern FPGAs. In the case of multiple 2D filters, the proposed algorithm also exploits any redundancy that exists within each filter and between different filters in the set, leading to designs with minimized area. Experiments with real filter sets from computer vision applications demonstrate an average of up to 38% reduction in the required area.

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  1. Synthesis and Optimization of 2D Filter Designs for Heterogeneous FPGAs

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            Vivek Venugopal

            Various techniques have been explored to implement hardware-efficient filters on field-programmable gate array (FPGA) devices in image processing applications [1]. Bouganis et al. describe some of the coefficient representation methods, such as canonical signed digit (CSD), minimal signed digit (MSD), partial subexpression evaluation, and singular value decomposition (SVD). The authors present an algorithm to implement two-dimensional (2D) filters, using the SVD representation method. The evaluation of the algorithm with respect to cost, area, and power is explained in detail. The algorithm is implemented on both Xilinx and Altera devices. The authors do not explain how Altera devices were modified in order to outperform the Xilinx devices. It would be interesting to see a metric for this specific comparison, in terms of hardware usage and design effort. Overall, the paper could be useful to both beginner and advanced digital signal processing (DSP) users who are researching hardware-efficient implementation methods for image processing applications. Online Computing Reviews Service

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            • Published in

              cover image ACM Transactions on Reconfigurable Technology and Systems
              ACM Transactions on Reconfigurable Technology and Systems  Volume 1, Issue 4
              January 2009
              161 pages
              ISSN:1936-7406
              EISSN:1936-7414
              DOI:10.1145/1462586
              Issue’s Table of Contents

              Copyright © 2009 ACM

              Publisher

              Association for Computing Machinery

              New York, NY, United States

              Publication History

              • Published: 1 January 2009
              • Accepted: 1 September 2008
              • Revised: 1 August 2008
              • Received: 1 November 2007
              Published in trets Volume 1, Issue 4

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