ABSTRACT
We study modular, automatic code generation from hierarchical block diagrams with synchronous semantics. Such diagrams are the fundamental model behind widespread tools in the embedded software domain, such as Simulink and SCADE. Code is modular in the sense that it is generated for a given composite block independently from context (i.e., without knowing in which diagrams the block is to be used) and using minimal information about the internals of the block. In previous work, we have shown how modular code can be generated by computing a set of interface functions for each block and a set of dependencies between these functions that is exported along with the interface. We have also introduced a quantified notion of modularity in terms of the number of interface functions generated per block, and showed how to minimize this number, which is essential for scalability. Finally, we have exposed the fundamental trade-off between modularity and reusability (set of diagrams the block can be used in).
In this paper we explore another trade-off: modularity vs. code size. We show that our previous technique, although it achieves maximal reusability and is optimal in terms of modularity, may result in code replication and therefore large code sizes, something often unacceptable in an embedded system context. We propose to remedy this by generating code with no replication, and show that this generally results in some loss of modularity. We show that optimizing modularity while maintaining maximal reusability and zero replication is an intractable problem (NP-complete). We also show that this problem can be solved using a simple iterative procedure that checks satisfiability of a sequence of propositional formulas. We report on a new prototype implementation and experimental results. The latter demonstrate the practical interest in our methods.
- P. Aubry, P. Le Guernic, and S. Machard. Synchronous distribution of Signal programs. In 29th Intl. Conf. Sys. Sciences, pages 656--665. IEEE, 1996. Google Scholar
Digital Library
- A. Benveniste, P. Caspi, S.A. Edwards, N. Halbwachs, P. Le Guernic, and R. de Simone. The synchronous languages 12 years later. Proc. IEEE, 91(1):64--83, January 2003.Google Scholar
- A. Benveniste, P. Le Guernic, and P. Aubry. Compositionality in dataflow synchronous languages: specification & code generation. Technical Report 3310, Irisa - Inria, 1997.Google Scholar
- G. Berry and G. Gonthier. The Esterel synchronous programming language: Design, semantics, implementation. Science of Computer Programming, 19(2):87--152, 1992. Google Scholar
Digital Library
- D. Biernacki, J-L. Colaco, G. Hamon, and M. Pouzet. Clock directed modular code generation for synchronous data-flow languages. In 2008 ACM SIGPLAN-SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES08). ACM, 2008. Google Scholar
Digital Library
- P. Caspi, D. Pilaud, N. Halbwachs, and J. Plaice. Lustre: a declarative language for programming synchronous systems. In 14th ACM Symp. POPL, 1987. Google Scholar
Digital Library
- D. Coppersmith and S. Winograd. Matrix multiplication via arithmetic progressions. J. Symbolic Comput., 9:251--280, 1990. Google Scholar
Digital Library
- S. Edwards and E. Lee. The semantics and execution of a synchronous block-diagram language. Science of Computer Programming, 48:21--42(22), July 2003. Google Scholar
Digital Library
- M. Fischer and A. Meyer. Boolean matrix multiplication and transitive closure. IEEE 12th Symp. on Switching and Automata Theory, pages 129--131, 1971. Google Scholar
Digital Library
- R.W. Floyd. Algorithm 97: Shortest path. Commun. ACM, 5(6):345, 1962. Google Scholar
Digital Library
- M.R. Garey and D.S. Johnson. Computers and Intractability. Freeman, 1978.Google Scholar
- O. Hainque, L. Pautet, Y. Le Biannic, and E. Nassor. Cronos: A Separate Compilation Toolset for Modular Esterel Applications. In World Congress on Formal Methods (FM\u201999), pages 1836--1853. Springer, 1999. Google Scholar
Digital Library
- E.A. Lee and H. Zheng. Leveraging synchronous language principles for heterogeneous modeling and design of embedded systems. In EMSOFT07: Proc. 7th ACM & IEEE Intl. Conf. on Embedded software, pages 114--123. ACM, 2007. Google Scholar
Digital Library
- R. Lublinerman and S. Tripakis. Modular Code Generation from Triggered and Timed Block Diagrams. In 14th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS08). IEEE CS Press, April 2008. Google Scholar
Digital Library
- R. Lublinerman and S. Tripakis. Modularity vs. Reusability: Code Generation from Synchronous Block Diagrams. In Design, Automation, and Test in Europe (DATE08). ACM, March 2008. Google Scholar
Digital Library
- O. Maffeis and P. Le Guernic. Distributed Implementation of Signal: Scheduling & Graph Clustering. In Formal Techniques in Real-Time and Fault-Tolerant Systems, pages 547--566. Springer, 1994. Google Scholar
Digital Library
- S. Malik. Analysis of cyclic combinational circuits. IEEE Trans. Computer-Aided Design, 13(7):950--956, 1994.Google Scholar
Digital Library
- P. Mosterman and J. Ciolfi. Interleaved execution to resolve cyclic dependencies in time-based block diagrams. In 43rd IEEE Conf. on Decision and Control (CDC04), 2004.Google Scholar
Cross Ref
- P. Raymond. Compilation separee de programmes Lustre. Master's thesis, IMAG, 1988. In French.Google Scholar
- T.R. Shiple, G. Berry, and H. Touati. Constructive analysis of cyclic circuits. In European Design and Test Conference (EDTC96). IEEE Computer Society, 1996. Google Scholar
Digital Library
- R. Tarjan. Depth-first search and linear graph algorithms. SIAM Journal on Computing, 1:146--160, 1972.Google Scholar
Digital Library
Index Terms
Modular code generation from synchronous block diagrams: modularity vs. code size
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Modular code generation from synchronous block diagrams: modularity vs. code size
POPL '09We study modular, automatic code generation from hierarchical block diagrams with synchronous semantics. Such diagrams are the fundamental model behind widespread tools in the embedded software domain, such as Simulink and SCADE. Code is modular in the ...
Modular Code Generation from Triggered and Timed Block Diagrams
RTAS '08: Proceedings of the 2008 IEEE Real-Time and Embedded Technology and Applications SymposiumIn previous work we have shown how modular code can be automatically generated from a synchronous block diagram notation where all blocks fire at all times. Here, we extend this work to triggered and timed diagrams, where some blocks fire only when ...
Clock-directed modular code generation for synchronous data-flow languages
LCTES '08: Proceedings of the 2008 ACM SIGPLAN-SIGBED conference on Languages, compilers, and tools for embedded systemsThe compilation of synchronous block diagrams into sequential imperative code has been addressed in the early eighties and can now be considered as folklore. However, separate, or modular, code generation, though largely used in existing compilers and ...







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