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Multi-core demands multi-interfaces

Published:14 February 2009Publication History

ABSTRACT

The challenge for the microarchitect has always been (with very few notable domain-specific exceptions) how to translate the continually increasing processing power provided by Moore's Law into increased performance, or more recently into similar performance at lower cost in energy. The mechanisms in the past (almost entirely) kept the interface intact and used the increase in transistor count to improve the performance of the microarchitecture of the uniprocessor. When that became too hard, we went to larger and larger on-chip caches. Both are consistent with the notion that "abstractions are good." At some point, we got overwhelmed with too many transistors; predictably, multi-core was born. As the transistor count continues to skyrocket, we are faced with two questions: what should be on the chip, and how should the software interface to it. If we expect to continue to take advantage of what process technology is providing, I think we need to do several things, starting with rethinking the notion of abstraction and providing multiple interfaces for the programmer.

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          • Published in

            cover image ACM Conferences
            PPoPP '09: Proceedings of the 14th ACM SIGPLAN symposium on Principles and practice of parallel programming
            February 2009
            322 pages
            ISBN:9781605583976
            DOI:10.1145/1504176
            • cover image ACM SIGPLAN Notices
              ACM SIGPLAN Notices  Volume 44, Issue 4
              PPoPP '09
              April 2009
              294 pages
              ISSN:0362-1340
              EISSN:1558-1160
              DOI:10.1145/1594835
              Issue’s Table of Contents

            Copyright © 2009 ACM

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            Association for Computing Machinery

            New York, NY, United States

            Publication History

            • Published: 14 February 2009

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