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PLAS 2008 paper abstracts
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Multiple-Valued Minimization to Optimize PLAs with Output EXOR Gates
ISMVL '99: Proceedings of the Twenty Ninth IEEE International Symposium on Multiple-Valued LogicThis paper considers an optimization method of programmable logic arrays (PLAs), which have two-input EXOR gate at the outputs. The PLA realizes an EXOR of two sum-of-products expressions (EX-SOP) for multiple-valued input two-valued output functions. ...
On the Optimal Design of Multiple-Valued PLAs
A description is given of the design and analysis of three types of multivalued PLAs (programmable logic arrays). Type 1 PLAs realize functions directly in the form of the max of min of literal functions and constants. In Type 2 PLAs, the body of the ...
Strongly Fault Secure PLAs and Totally Self-Checking Checkers
A general approach is presented to the design of totally self-checking (TSC) programmable logic arrays (PLAs). A strongly fault secure (SFS) implementation is suggested for the functional PLA, which is shown to be SFS whenever the output is encoded by ...






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