ABSTRACT
As VLSI technology moves to the 65nm node and beyond, interconnect delay greatly limits the circuit performance. As a critical component in interconnect synthesis, layer assignment manifests enormous potential in drastically reducing wire delay. This is due the fact that wires on thick metals are much less resistive than those on thin metals. Nevertheless, it is not desired to assign all wires to thick metals and the right strategy is to only use minimal thick-metal routing resources for meeting the timing constraints. This timing driven minimum cost layer assignment problem is NP-Complete, and a fast algorithm with provable approximation bound is highly desired.
In this paper, a new fully polynomial time approximation scheme is proposed. It is based on a linear-time dynamic programming algorithm for bounded-cost layer assignment and efficient oracle queries. The proposed algorithm can approximate the optimal layer assignment solution in O(mn2/ε) time within a factor of 1+ε for any ε>0, where n is the tree size and m is the number of routing layers. This significantly improves the previous work. The new algorithm is also highly practical. Our experiments on industrial netlists demonstrate that the new algorithm runs up to 6.5times faster than the optimal dynamic programming with few percent additional wire as guaranteed theoretically. This gives another 2x speedup over the previous work.
- S. Hu, Z. Li, and C. Alpert, "A polynomial time approximation scheme for timing constrained minimum cost layer assignment," in ICCAD, 2008. Google Scholar
Digital Library
- Z. Li, C. Alpert, S. Hu, T. Muhmud, S. Quay, and P. Villarrubia,"Fast interconnect synthesis with layer assignment," in ISPD, 2008. Google Scholar
Digital Library
- J. Fishburn and C. Schevon, "Shaping a distributed-rc line to minimize elmore delay," IEEE Trans. on Circuits and Systems-I, vol. 42, no. 12, pp. 1020--1022, 1995.Google Scholar
Cross Ref
- C.--P. Chen, C. Chu, and D. Wong, "Fast and exact simultaneous gate and wire sizing by lagrangian relaxation," IEEE Transactions on Computer-Aided Design, vol. 18, no. 7, pp. 1014--1025, 1999. Google Scholar
Digital Library
- J. Cong, K.-S. Leung, and D. Zhou, "Performance-driven interconnect design based on distributed rc delay model," in DAC, pp. 606--611, 1993. Google Scholar
Digital Library
- J. Cong and K.-S. Leung, "Optimal wire sizing under elmore delay model," IEEE Transactions on Computer-Aided Design, vol. 14, no. 3, pp. 321--336, 1995. Google Scholar
Digital Library
- C. Alpert, A. Devgan, J. P. Fishburn, and S. T. Quay, "Interconnect synthesis without wire tapering," IEEE Transactions on Computer-Aided Design, vol. 20, no. 1, pp. 90--104, 2001. Google Scholar
Digital Library
- J. Lillis and C.-K. Cheng and T.-T.Y. Lin, "Optimal wire sizing and buffer insertion for low power and a generalized delay model," IEEE Journal of Solid State Circuits, vol. 31, no. 3, pp. 437--447, 1996.Google Scholar
Cross Ref
- L.P.P.P. van Ginneken, "Buffer placement in distributed RC-tree networks for minimal Elmore delay," in Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 865--868,1990.Google Scholar
Cross Ref
- C. Alpert, S. Karandikar, Z. Li, G.-J. Nam, S. Quay, H.Ren, C. Sze, P. Villarrubia, and M. Yildiz, "Techniques for fast physical synthesis," Proceedings of IEEE, vol. 95, no. 3, pp. 573--599, 2007.Google Scholar
Cross Ref
- R. Hassin, "Approximation schemes for the restricted shortest path problem," Mathematics of Operations Research, vol. 17, no. 1, pp. 36--42, 1992. Google Scholar
Digital Library
- S. Hu, C. J. Alpert, J. Hu, S. Karandikar, Z. Li, W. Shi, and C. N.Sze, "Fast algorithms for slew constrained minimum cost buffering," IEEE Transactions on Computer-Aided Design, vol. 26, no. 11, pp. 2009--2022, 2007. Google Scholar
Digital Library
- Z. Li and W. Shi, "An O(bn
2ε) time algorithm for optimal buffer insertion with b buffer types," IEEE Transactions on Computer-Aided Design, vol. 25, no. 3, pp. 484--489, 2006. Google Scholar
Digital Library
- W. Shi, Z. Li and C. J. Alpert, "Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost," in ASPDAC, pp. 609--614, 2004. Google Scholar
Digital Library
- F. Ergun and R. Sinha and L. Zhang, "An improved FPTAS for restricted shortest path," Information Processing Letters,Vol. 83, No. 5, pp. 287--291, 2002. Google Scholar
Digital Library
Index Terms
A faster approximation scheme for timing driven minimum cost layer assignment
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