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Recurrence cycle aware modulo scheduling for coarse-grained reconfigurable architectures

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Published:19 June 2009Publication History
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Abstract

In high-end embedded systems, coarse-grained reconfigurable architectures (CGRA) continue to replace traditional ASIC designs. CGRAs offer high performance at a low power consumption, yet provide flexibility through programmability. In this paper we introduce a recurrence cycle-aware scheduling technique for CGRAs. Our modulo scheduler groups operations belonging to a recurrence cycle into a clustered node and then computes a scheduling order for those clustered nodes. Deadlocks that arise when two or more recurrence cycles depend on each other are resolved by using heuristics that favor recurrence cycles with long recurrence delays. While with previous work one had to sacrifice either a fast compilation speed in order to get good quality results, or vice versa, this is not necessary anymore with the proposed recurrence cycle-aware scheduling technique. We have implemented the proposed method into our in-house CGRA chip and compiler solution and show that the technique achieves better quality schedules than schedulers based on simulated annealing at a 170-fold speed increase.

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          • Published in

            cover image ACM SIGPLAN Notices
            ACM SIGPLAN Notices  Volume 44, Issue 7
            LCTES '09
            July 2009
            176 pages
            ISSN:0362-1340
            EISSN:1558-1160
            DOI:10.1145/1543136
            Issue’s Table of Contents
            • cover image ACM Conferences
              LCTES '09: Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
              June 2009
              188 pages
              ISBN:9781605583563
              DOI:10.1145/1542452

            Copyright © 2009 ACM

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            New York, NY, United States

            Publication History

            • Published: 19 June 2009

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