Abstract
Embedded systems, like general-purpose systems, can benefit from parallel execution on a symmetric multicore platform. Unfortunately, concurrency issues present in general-purpose programming also apply to embedded systems, protection from which is currently only offered with performance-limiting coarse-grained locking or error-prone and difficult-to-implement fine-grained locking. Transactional memory offers relief from these mechanisms, but has primarily been investigated on general-purpose systems. In this paper, we present Embedded Software Transactional Memory (ESTM) as a novel solution to the concurrency problem in parallel embedded applications. We investigate common software transactional memory design decisions and discuss the best decisions for an embedded platform. We offer a full implementation of an embedded STM and test it against both coarse-grained and fine-grained locking mechanisms. We find that we can meet or beat the performance of fine-grained locking over a range of application characteristics, including size of shared data, time spent in the critical section, and contention between threads. Our ESTM implementation benefits from the effective use of L1 memory, a feature which is built into our STM model but which cannot be directly utilized by traditional locking mechanisms.
- Adl--Tabatabai, A.-R., Lewis, B. T., Menon, V., Murphy, B. R., Saha, B., and Shpeisman, T. Compiler and runtime support for efficient software transactional memory. In PLDI '06: Proceedings of the 2006 ACM SIGPLAN conference on Programming Language Design and Implementation (2006), ACM, pp. 26--37. Google Scholar
Digital Library
- Analog Devices, Inc. ADSP-BF53x/BF56x Blackfin Processor Programming Reference, revision 1.2 ed. One Technology Way, Norwood, Mass, 02062, February 2007.Google Scholar
- Analog Devices, Inc. ADSP-BF561 Blackfin Processor Hardware Reference, revision 1.1 ed. One Technology Way, Norwood, Mass, 02062, February 2007.Google Scholar
- Analog Devices, Inc. Visual DSP 5.0 Kernel (VDK) User's Guide, revision 3.0 ed. One Technology Way, Norwood, Mass, 02062, August 2007.Google Scholar
- Ananian, C. S., Asanovic, K., Kuszmaul, B. C., Leiserson, C. E., and Lie, S. Unbounded transactional memory. In HPCA '05: Proceedings of the 11th International Symposium on High--Performance Computer Architecture (2005), pp. 316--327. Google Scholar
Digital Library
- Anderson, J. H., and Moir, M. Universal constructions for multi-object operations. In PODC'95: Proceedings of the fourteenth annual ACM symposium on Principles of distributed computing (1995), ACM, pp. 184--193. Google Scholar
Digital Library
- Anderson, J. H., Ramamurthy, S., and Jain, R. Implementing wait-free objects on priority-based systems. In PODC'97: Proceedings of the sixteenth annual ACM symposium on Principles of distributed computing (1997), ACM, pp. 229--238. Google Scholar
Digital Library
- Avissar, O., Barua, R., and Stewart, D. An optimal memory allocation scheme for scratch-pad-based embedded systems. ACM Transactions on Embedded Computing Systems 1 (2002), 6--26. Google Scholar
Digital Library
- Baugh, L., Neelakantam, N., and Zilles, C. Using hardware memory protection to build a high-performance, strongly-atomic hybrid transactional memory. In ISCA'08: Proceedings of the 35th International Symposium on Computer Architecture (2008). Google Scholar
Digital Library
- Blundell, C., Devietti, J., Lewis, E. C., and Martin, M. M. K. Making the fast case common and the uncommon case simple in unbounded transactional memory. In ISCA'07: Proceedings of the 34th annual international symposium on Computer architecture (2007). Google Scholar
Digital Library
- Crowl, L., Lev, Y., Luchangco, V., Moir, M., and Nussbaum, D. Integrating transactional memory into C. In TRANSACT'07: ACM SIGPLAN Workshop on Transactional Computing (2007), ACM.Google Scholar
- Damron, P., Fedorova, A., Lev, Y., Luchangco, V., Moir, M., and Nussbaum, D. Hybrid transactional memory. In ASPLOS--XII: Proceedings of the 12th international conference on Architectural support for programming languages and operating systems (October 2006), ACM, pp. 336--346. Google Scholar
Digital Library
- Dice, D., Shalev, O., and Shavit, N. Transactional locking II. In DISC'06: Proceedings of the 20th International Symposium on Distributed Computing (September 2006), ACM, pp. 194--208. Google Scholar
Digital Library
- Dice, D., and Shavit, N. Understanding tradeoffs in software transactional memory. In CGO'07: Proceedings of the International Symposium on Code Generation and Optimization (2007), IEEE Computer Society, pp. 21--33. Google Scholar
Digital Library
- Egger, B., Kim, C., Jang, C., Nam, Y., Lee, J., and Min, S. L. A dynamic code placement technique for scratchpad memory using postpass optimization. In CASES (October 2006), ACM. Google Scholar
Digital Library
- Ennals, R. Software transactional memory should not be obstruction-free. Tech. Rep. IRC-TR-06-052, Intel Research Cambridge, January 2006.Google Scholar
- Ferri, C., Moreshet, T., Bahar, I. R., Benini, L., and Herlihy, M. A hardware/software framework for supporting transactional memory in a MPSoC environment. SIGARCH Comput. Archit. News 35, 1 (2007), 47--54. Google Scholar
Digital Library
- Francesco, P., Marchal, P., Atienza, D., Benini, L., Catthoor, F., and Mendias, J. M. An integrated hardware/software approach for run-time scratchpad management. In DAC '04: Proceedings of the 41st annual conference on Design automation (2004), ACM. Google Scholar
Digital Library
- Fraser, K., and Harris, T. Concurrent programming without locks. ACM Transactions on Computer Systems 25, 2 (May 2007). Google Scholar
Digital Library
- Hammond, L., Wong, V., Chen, M., Carlstrom, B. D., Davis, J. D., Hertzberg, B., Prabhu, M. K., Wijaya, H., Kozyrakis, C., and Olukotun, K. Transactional memory coherence and consistency. In ISCA'04: Proceedings of the 31st Annual Internation Symposium on Computer Architecture (2004), IEEE Computer Society. Google Scholar
Digital Library
- Harris, T., and Fraser, K. Language support for lightweight transactions. In OOPSLA'03: Proceedings of the 18th annual ACM SIGPLAN conference on Object-oriented programing, systems, languages, and applications (2003), ACM, pp. 388--402. Google Scholar
Digital Library
- Harris, T., Plesko, M., Shinnar, A., and Tarditi, D. Optimizing memory transactions. In PLDI'06: Proceedings of the 2006 ACM SIGPLAN conference on Programming language design and implementation (2006), ACM, pp. 14--25. Google Scholar
Digital Library
- Herlihy, M. A methodology for implementing highly concurrent data objects. ACM Trans. Program. Lang. Syst. 15, 5 (1993), 745--770. Google Scholar
Digital Library
- Herlihy, M., Luchangco, V., and Moir, M. A flexible framework for implementing software transactional memory. In OOPSLA'06: Proceedings of the 21st annual ACM SIGPLAN conference on Object-oriented programming systems, languages, and applications (2006), ACM, pp. 253--262. Google Scholar
Digital Library
- Herlihy, M., Luchangco, V., Moir, M., and III, W. N. S. Software transactional memory for dynamic-sized data structures. In PODC'03: Proceedings of the 22nd Annual Symposium on Principles of Distributed Computing (July 2003), ACM, pp. 92--101. Google Scholar
Digital Library
- Herlihy, M., and Moss, J. E. B. Transactional memory: Architectural support for lock-free data structures. In ISCA '93: Proceedings of the 20th Annual International Symposium on Computer Architecture (1993), ACM, pp. 289--300. Google Scholar
Digital Library
- Kumar, T. R., Govindarajan, R., and Kumar, C. R. Optimal code and data layout in embedded systems. In 16th International Conference on VLSI Design (VLSI) (2003), IEEE. Google Scholar
Digital Library
- Marathe, V. J., III, W. N. S., and Scott, M. L. Adaptive software transactional memory. In DISC 19: In Proceedings of the 19th International Symposium on Distributed Computing (2005). Google Scholar
Digital Library
- Marathe, V. J., Scherer, W. N., and Scott, M. L. Design tradeoffs in modern software transactional memory systems. In LCR'04: Proceedings of the 7th workshop on Workshop on languages, compilers, and run-time support for scalable systems (2004), ACM, pp. 1--7. Google Scholar
Digital Library
- Marathe, V. J., Spear, M. F., Heriot, C., Acharya, A., Eisenstat, D., III, M. N. S., and Scott, M. L. Lowering the overhead of nonblocking software transactional memory. In TRANSACT'06: ACM SIGPLAN Workshop on Transactional Computing (June 2006), ACM.Google Scholar
- Moir, M. Transparant support for wait-free transactions. In Proceedings of the 11th International Workshop on Distributed Algorithms (1997). Google Scholar
Digital Library
- Monchiero, M., Palermo, G., Silvano, C., and Villa, O. Power/performance hardware optimization for synchronization intensive applications in MPSoCs. In DATE'06: Proceedings of the conference on Design, automation and test in Europe (2006). Google Scholar
Digital Library
- Moore, K., Bobba, J., Moravan, M., Hill, M., and Wood, D. Log': Log-based transactional memory. In High-Performance Computer Architecture, 2006. The Twelfth International Symposium on (Feb. 2006).Google Scholar
Cross Ref
- Panda, P. R., Dutt, N. D., and Nicolau, A. Efficient utilization of scratch-pad memory in embedded processor applications. In European Design Automation and Test Conference (March 1997), IEEE, pp. 7--11. Google Scholar
Digital Library
- Saha, B., Adl-Tabatabai, A.-R., Hudson, R. L., Minh, C. C., and Hertzberg, B. McRT-S': A high performance software transactional memory system for a multi-core runtime. In PPoPP '06: Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice of parallel programming (2006), ACM, pp. 187--197. Google Scholar
Digital Library
- Saha, B., Adl-Tabatabai, A.-R., and Jacobson, Q. Architectural support for software transactional memory. In MICRO 39: Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (2006), IEEE Computer Society, pp. 185--196. Google Scholar
Digital Library
- Shavit, N., and Touitou, D. Software transactional memory. In PODC'95: Proceedings of the 14th Symposium on the Principles of Distributed Computing (1995), ACM Press. Google Scholar
Digital Library
Index Terms
Software transactional memory for multicore embedded systems
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