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A-Port Networks: Preserving the Timed Behavior of Synchronous Systems for Modeling on FPGAs

Published:01 September 2009Publication History
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Abstract

Computer architects need to run cycle-accurate performance models of processors orders of magnitude faster. We discuss why the speedup on traditional multicores is limited, and why FPGAs represent a good vehicle to achieve a dramatic performance improvement over software models. This article introduces A-Port Networks, a simulation scheme designed to expose the fine-grained parallelism inherent in performance models and efficiently exploit them using FPGAs.

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    • Published in

      cover image ACM Transactions on Reconfigurable Technology and Systems
      ACM Transactions on Reconfigurable Technology and Systems  Volume 2, Issue 3
      September 2009
      121 pages
      ISSN:1936-7406
      EISSN:1936-7414
      DOI:10.1145/1575774
      Issue’s Table of Contents

      Copyright © 2009 ACM

      Publisher

      Association for Computing Machinery

      New York, NY, United States

      Publication History

      • Published: 1 September 2009
      • Accepted: 1 July 2008
      • Received: 1 June 2008
      Published in trets Volume 2, Issue 3

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