Abstract
Coupling reconfigurable hardware accelerators with processors is an effective way to meet the performance and flexibility required to cope with modern embedded applications. The ARISE framework provides a systematic approach to extend a processor once. It will thereafter support the coupling of arbitrary hardware accelerators. The accelerators can be coupled as coprocessors or functional units of the processor’s datapath, and therefore exploited as a hybrid, which includes both loose and tight computational models. This article presents a complete framework for developing applications on such hybrid reconfigurable ARISE machines. The framework integrates the automatic identification of custom instructions and the semiautomatic/profiling-driven identification of coprocessors supporting the hybrid computational model. Moreover, it supports a modular design approach where the software and the hardware modules are developed independently and later ported into any ARISE machine with reconfigurable technology. To evaluate efficiency, a set of benchmarks is implemented on an ARISE evaluation machine utilizing the proposed framework. In addition, the ARISE machine is compared against a well-established processor paradigm that utilizes reconfigurable accelerators following only the typical coprocessor approach. Experimental results prove that the framework can be used to exploit the hybrid computational model and achieve significant performance improvements over the typical coprocessor acceleration approach. Moreover, results demonstrate how the framework can be used to trade off performance, silicon area, and application development time.
- <scp>Alippi, C., Fornaciari, W., Pozzi, L., and Sami, M.</scp> 1999. A DAG-based design approach for reconfigurable VLIW processors. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE’99). ACM, New York, 57. Google Scholar
Digital Library
- <scp>Atasu, K., Ozturan, C., Dundar, G., Mencer, O., and Luk, W.</scp> 2008. CHIPS: Custom hardware instruction processor synthesis. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 27, 3, 528--541. Google Scholar
Digital Library
- <scp>Atasu, K., Pozzi, L., and Ienne, P.</scp> 2003. Automatic application-specific instruction-set extensions under microarchitectural constraints. Int. J. Para. Prog. 31, 6, 411--428. Google Scholar
Digital Library
- <scp>Barat, F., Lauwereins, R., and Deconinck, G.</scp> 2002. Reconfigurable instruction set processors from a hardware/software perspective. IEEE Trans. Softw. Eng. 28, 9, 847--862. Google Scholar
Digital Library
- <scp>Bracy, A., Prahlad, P., and Roth, A.</scp> 2004. Dataflow mini-graphs: amplifying superscalar capacity and bandwidth. In Proceedings of the 37th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO’37). 18--29. Google Scholar
Digital Library
- <scp>Brisk, P., Kaplan, A., Kastner, R., and Sarrafzadeh, M.</scp> 2002. Instruction generation and regularity extraction for reconfigurable processors. In Proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES’02). ACM, New York, 262--269. Google Scholar
Digital Library
- <scp>Clark, N., Blome, J., Chu, M., Mahlke, S., Biles, S., and Flautner, K.</scp> 2005. An architecture framework for transparent instruction set customization in embedded processors. In Proceedings of the 32nd International Symposium on Computer Architecture (ISCA’05). 272--283. Google Scholar
Digital Library
- <scp>Fritts, J. E., Steiling, F. W., and Tucek, J. A.</scp> 2005. Mediabench II video: expediting the next generation of video systems research. In SPIE Electronic Imaging---Embedded Processors for Multimedia and Communications II. 77--93.Google Scholar
- <scp>Goodwin, D. and Petkov, D.</scp> 2003. Automatic generation of application specific processors. In Proceedings of the International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES’03). 137--147. Google Scholar
Digital Library
- <scp>Gupta, S., Dutt, N., Gupta, R., and Nicolau, A.</scp> 2003. SPARK: A high-level synthesis framework for applying parallelizing compiler transformations. In Proceedings of the 16th International Conference on VLSI Design. 461--466. Google Scholar
Digital Library
- <scp>Guthaus, M. R., Ringenberg, J. S., Ernst, D., Austin, T. M., Mudge, T., and Brown, R. B.</scp> 2001. MiBench: A free, commercially representative embedded benchmark suite. In Proceedings of the IEEE International Workshop on Workload Characterization (WWC’01). 3--14. Google Scholar
Digital Library
- <scp>Hartenstein, R.</scp> 2001. A decade of reconfigurable computing: A visionary retrospective. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE’01). 642--649. Google Scholar
Digital Library
- <scp>Hauck, S., Fry, T. W., Hosler, M. M., and Kao, J. P.</scp> 2004. The chimaera reconfigurable functional unit. IEEE Trans. VLSI Syst. 12, 2, 206--217. Google Scholar
Digital Library
- <scp>Hauser, J. R. and Wawrzynek, J.</scp> 1997. Garp: A MIPS processor with a reconfigurable coprocessor. In Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines. 12--21. Google Scholar
Digital Library
- <scp>Lodi, A., Toma, M., Campi, F., Cappelli, A., Canegallo, R., and Guerrieri, R.</scp> 2003. A VLIW processor with reconfigurable instruction set for embedded applications. IEEE J. Solid-State Circ. 38, 11, 1876--1886.Google Scholar
Cross Ref
- <scp>Micheli, G. D., Ernst, R., and Wolf, W.</scp>, Eds. 2002. Readings in Hardware/Software Co-Design. Kluwer Academic Publishers, Norwell, MA. Google Scholar
Digital Library
- <scp>Miyamori, T. and Olukotun, K.</scp> 1998. REMARC: Reconfigurable multimedia array coprocessor (abstract). In Proceedings of the ACM/SIGDA 6th International Symposium on Field Programmable Gate Arrays (FPGA). 261. Google Scholar
Digital Library
- <scp>Pozzi, L., Atasu, K., and Ienne, P.</scp> 2006. Exact and approximate algorithms for the extension of embedded processor instruction sets. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 25, 7, 1209--1229. Google Scholar
Digital Library
- <scp>Sassone, P. G. and Wills, D. S.</scp> 2004. Dynamic strands: collapsing speculative dependence chains for reducing pipeline communication. In Proceedings of the 37th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO’37). 7--17. Google Scholar
Digital Library
- <scp>Scott, J., Lee, L., Arends, J., and Moyer, B.</scp> 1998. Designing the low-power M*CORE architecture. In Proceedings of the International Symposium on Computer Architecture Power Driven Microarchitecture Workshop. 145--150.Google Scholar
- <scp>Shoa, A. and Shirani, S.</scp> 2005. Run-time reconfigurable systems for digital signal processing applications: A survey. J. VLSI Sig. Process. Syst. 39, 3, 213--235.Google Scholar
Digital Library
- <scp>Singh, H., Lee, M.-H., Lu, G., Kurdahi, F. J., Bagherzadeh, N., and Filho, E. M. C.</scp> 2000. MorphoSys: An integrated reconfigurable system for data-parallel and computation-intensive applications. IEEE Trans. Comput. 49, 5, 465--481. Google Scholar
Digital Library
- <scp>Sun, F., Ravi, S., Raghunathan, A., and Jha, N. K.</scp> 2002. Synthesis of custom processors based on extensible platforms. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD’02). 641--648. Google Scholar
Digital Library
- <scp>Vassiliadis, N., Theodoridis, G., and Nikolaidis, S.</scp> 2009. The ARISE approach for extending embedded processors with arbitrary hardware accelerators. IEEE Trans. VLSI Syst. 17, 2, 221--233. Google Scholar
Digital Library
- <scp>Vassiliadis, N., Theodoridis, G., and Nikolaidis, S.</scp> 2007. The ARISE reconfigurable instruction set extensions framework. In Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS’07). 153--160.Google Scholar
- <scp>Vassiliadis, N., Theodoridis, G., and Nikolaidis, S.</scp> 2008. ARISE machines: extending processors with hybrid accelerators. In Proceedings of the International Workshop on Applied Reconfigurable Computing. Google Scholar
Digital Library
- <scp>Vassiliadis, N., Theodoridis, G., and Nikolaidis, S.</scp> 2006. An automated development framework for a RISC processor with reconfigurable instruction set extensions. In Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS’06). Google Scholar
Digital Library
- <scp>Vassiliadis, S., Wong, S., Gaydadjiev, G., Bertels, K., Kuzmanov, G., and Panainte, E.</scp> 2004. The MOLEN polymorphic processor. IEEE Trans. Comput. 53, 11, 1363--1375. Google Scholar
Digital Library
- <scp>Wittig, R. and Chow, P.</scp> 1996. OneChip: an FPGA processor with reconfigurable logic. In Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines. 126--135.Google Scholar
- <scp>Yehia, S. and Temam, O.</scp> 2004. From sequences of dependent instructions to functions: an approach for improving performance without ILP or speculation. In Proceedings of the 31st Annual International Symposium on Computer Architecture (ISCA’04). 238. Google Scholar
Digital Library
- <scp>Yu, P. and Mitra, T.</scp> 2004. Characterizing embedded applications for instruction-set extensible processors. In Proceedings of the 41st Annual Conference on Design Automation (DAC’04). 723--728. Google Scholar
Digital Library
Index Terms
An Application Development Framework for ARISE Reconfigurable Processors
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