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An efficient transactional memory algorithm for computing minimum spanning forest of sparse graphs

Published:14 February 2009Publication History
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Abstract

Due to power wall, memory wall, and ILP wall, we are facing the end of ever increasing single-threaded performance. For this reason, multicore and manycore processors are arising as a new paradigm to pursue. However, to fully exploit all the cores in a chip, parallel programming is often required, and the complexity of parallel programming raises a significant concern. Data synchronization is a major source of this programming complexity, and Transactional Memory is proposed to reduce the difficulty caused by data synchronization requirements, while providing high scalability and low performance overhead.

The previous literature on Transactional Memory mostly focuses on architectural designs. Its impact on algorithms and applications has not yet been studied thoroughly. In this paper, we investigate Transactional Memory from the algorithm designer's perspective. This paper presents an algorithmic model to assist in the design of efficient Transactional Memory algorithms and a novel Transactional Memory algorithm for computing a minimum spanning forest of sparse graphs. We emphasize multiple Transactional Memory related design issues in presenting our algorithm. We also provide experimental results on an existing software Transactional Memory system. Our algorithm demonstrates excellent scalability in the experiments, but at the same time, the experimental results reveal the clear limitation of software Transactional Memory due to its high performance overhead. Based on our experience, we highlight the necessity of efficient hardware support for Transactional Memory to realize the potential of the technology.

References

  1. C. S. Ananian, K. Asanovic, B. C. Kuszmaul, C. E. Leiserson, and S. Lie. Unbounded transactional memory. In Proc. 11th Int'l Conf. on High-Performance Computer Architecture (HPCA), San Francisco, CA, Feb. 2005. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. K. Asanovic, R. Bodik, B. C. Catanzaro, J. J. Gebis, P. Husbands, K. Keutzer, D. A. Patterson, W. L. Plishker, J. Shalf, S. W. Williams, and K. A. Yelick. The landscape of parallel computing research: A view from berkeley. Technical Report UCB/EECS-2006-183, Electrical Engineering and Computer Sciences, University of California at Berkeley, Dec. 2006.Google ScholarGoogle Scholar
  3. D. A. Bader and G. Cong. Fast shared-memory algorithms for computing the minimum spanning forest of sparse graphs. Journal of Parallel and Distributed Computing, 66(11), 2006. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. D. A. Bader and K. Madduri. SNAP, small-world network analysis and partitioning: an open-source parallel graph framework for the exploration of large-scale networks. In Proc. 22nd Int'l Parallel and Distributed Processing Symp. (IPDPS), Miami, FL, Apr. 2008.Google ScholarGoogle ScholarCross RefCross Ref
  5. C. Blundell, J. Devietti, E. C. Lewis, and M. M. K. Martin. Making the fast case common and the uncommon case simple in unbounded transactional memory. In Proc. 34th Ann. Int'l Symp. on Computer Architecture (ISCA), San Diego, CA, Jun. 2007. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. C. Blundell, E. C. Lewis, and M. M. K. Martin. Deconstructing transactional semantics: The subtleties of atomicity. In Proc. 4th Ann. Workshop on Duplicating, Deconstructing, and Debunking (WDDD), Madison, WI, Jun. 2005.Google ScholarGoogle Scholar
  7. J. Chung, C. C. Minh, B. D. Carlstrom, and C. Kozyrakis. Parallelizing SPECjbb2000 with transactional memory. In In Proc. Workshop on Transactional Memory Workloads (WTW), Ottawa, Canada, Jun. 2006.Google ScholarGoogle Scholar
  8. P. Damron, A. Fedorova, Y. Lev, V. Luchangco, M. Moir, and D. Nussbaum. Hybrid transactional memory. In Proc. 12th Int'l Conf. on Architecture Support for Programming Languages and Operating Systems (ASPLOS), San Jose, CA, Oct. 2006. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. D. Dice, M. Herlihy, D. Lea, Y. Lev, V. Luchangco, W. Mesard, M. Moir, K. Moore, and D. Nussbaum. Applications of the adaptive transactional memory test platform. In Proc. 3rd ACM SIGPLAN Workshop on Transactional Computing (TRANSACT), Salt Lake City, UT, Feb. 2008.Google ScholarGoogle Scholar
  10. D. Dice, O. Shalev, and N. Shavit. Transactional locking II. In Proc. 20th Int'l Symp. on Distributed Computing (DISC), Stockholm, Sweden, Sep 2006. Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. R. Guerraoui, M. Kapalka, and J. Vitek. STMBench7: a benchmark for software transactional memory. In Proc. 2nd ACM SIGOPS/EuroSys European Conf. on Computer Systems (EuroSys), Lisbon, Portugal, Mar. 2007. Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. L. Hammond, V. Wong, M. Chen, B. D. Carlstrom, J. D. Davis, B. Hertzberg, M. K. Prabhu, H. Wijaya, C. Kozyrakis, and K. Olukotun. Transactional memory coherence and consistency. In Proc. 31st Ann. Int'l Symp. on Computer Architecture (ISCA), Munich, Germany, Jun. 2004. Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. T. Harris, S. Marlow, S. P. Jones, and M. Herlihy. Composable memory transactions. In Proc. 10th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), Chicago, IL, Jun. 2005. Google ScholarGoogle ScholarDigital LibraryDigital Library
  14. M. Herlihy, J. Eliot, and B. Moss. Transactional memory: Architectural support for lock-free data structures. In Proc. 20th Ann. Int'l Symp. on Computer Architecture (ISCA), New York, NY, May 1993. Google ScholarGoogle ScholarDigital LibraryDigital Library
  15. M. Herlihy, V. Luchangco, M. Moir, and W. N. Scherer III. Software transactional memory for dynamic-sized data structures. In Proc. 22nd Ann. Symp. on Principle of Distributed Computing (PODC), Boston, MA, Jul. 2003. Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. M. Kulkarni, K. Pingali, G. Ramanarayanan, B. Walter, K. Bala, and L. P. Chew. Optimistic parallelism benefits from data partitioning. In Proc. 13th Int'l Conf. on Architecture Support for Programming Languages and Operating Systems (ASPLOS), Seattle, WA, Mar. 2008. Google ScholarGoogle ScholarDigital LibraryDigital Library
  17. V. J. Marathe, W. N. Scherer III, and M. L. Scott. Adaptive software transactional memory. In Proc. 19th Int'l Symp. on Distributed Computing (DISC), Cracow, Poland, Mar. 2005. Google ScholarGoogle ScholarDigital LibraryDigital Library
  18. K. Mehlhorn and S. Näher. The LEDA platform of combinatorial and geometric computing. Communications of the ACM, 38(1):96--102, 1995. Google ScholarGoogle ScholarDigital LibraryDigital Library
  19. C. C. Minh, J. Chung, C. Kozyrakis, and K. Olukotun. STAMP: Stanford transactional applications for multi-processing. In Proc. 11th IEEE Int'l Symp. on Workload Characterization (IISWC), Seattle, WA, Sep. 2008.Google ScholarGoogle Scholar
  20. C. C. Minh, M. Trautmann, J. Chung, A. McDonald, N. Bronson, J. Casper, C. Kozyrakis, and K. Olukotun. An effective hybrid transactional memory system with strong isolation guarantees. In Proc. 34th Ann. Int'l Symp. on Computer Architecture (ISCA), San Diego, CA, Jun. 2007. Google ScholarGoogle ScholarDigital LibraryDigital Library
  21. K. E. Moore, J. Bobba, M. J. Moravan, M. D. Hill, and D. A. Wood. Log™: Log-based transactional memory. In Proc. 12th Int'l Conf. on High-Performance Computer Architecture (HPCA), Austin, TX, Feb. 2006.Google ScholarGoogle ScholarCross RefCross Ref
  22. B. M. E. Moret and H. D. Shapiro. An empirical assessment of algorithms for constructing a minimal spanning tree. In DIMACS Monographs in Discrete Mathematics and Theoretical Computer Science: Computational Support for Discrete Mathematics 15, pages 99--117. American Mathematical Society, 1994.Google ScholarGoogle Scholar
  23. C. Perfumo, N. Sonmez, S. Stipic, O. Unsal, A. Cristal, T. Harris, and M. Valero. The limits of software transactional memory (STM):dissecting Haskell STM applications on a many-core environment. In Proc. 5th ACM Int'l Conf. on Computing Frontiers (CF), Ischia, Italy, May 2008. Google ScholarGoogle ScholarDigital LibraryDigital Library
  24. R. Rajwar, M. Herlihy, and K. Lai. Virtualizing transactional memory. In Proc. 32nd Ann. Int'l Symp. on Computer Architecture (ISCA), Madison, WI, Jun. 2005. Google ScholarGoogle ScholarDigital LibraryDigital Library
  25. M. L. Scott, M. F. Spear, L. Dalessandro, and V. J. Marathe. Delaunay triangulation with transactions and barriers. In Proc. 10th IEEE Int'l Symp. on Workload Characterization (IISWC), Boston, MA, Sep. 2007. Google ScholarGoogle ScholarDigital LibraryDigital Library
  26. A. Shriraman, M. F. Spear, H. H., V. J. Marathe, S. Dwarkadas, and M. L. Scott. An integrated hardware-software approach to flexible transactional memory. In Proc. 34th Ann. Int'l Symp. on Computer Architecture (ISCA), San Diego, CA, Jun. 2007. Google ScholarGoogle ScholarDigital LibraryDigital Library
  27. M. Tremblay and S. Chaudhry. A third-generation 65nm 16-core 32-thread plus 32-scout-thread CMT SPARC processor. In Proc. Int'l Solid State Circuits Conf. (ISSCC), San Francisco, CA, Feb. 2008.Google ScholarGoogle ScholarCross RefCross Ref
  28. T. Vijaykumar, S. Gopal, J. E. Smith, and G. Sohi. Speculative versioning cache. In Proc. 5th Int'l Conf. on High-Performance Computer Architecture (HPCA), Las Vegas, NV, Jan. 1998. Google ScholarGoogle ScholarDigital LibraryDigital Library
  29. C. von Praun, R. Bordawekar, and C. Cascaval. Modeling optimistic concurrency using quantitative dependence analysis. In Proc. 13th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), Salt Lake City, UT, Feb. 2008. Google ScholarGoogle ScholarDigital LibraryDigital Library
  30. I. Watson, C. Kirkham, and M. Lujan. A study of a transactional parallel routing algorithm. In Proc. 16th Int'l Conf. on Parallel Architectures and Compilation Techniques (PACT), Brasov, Romania, Sep. 2007. Google ScholarGoogle ScholarDigital LibraryDigital Library
  31. Y. Zhang, L. Rauchwerger, and J. Torrellas. Hardware for speculative run-time parallelization in distributed shared-memory multiprocessors. In Proc. 5th Int'l Conf. on High-Performance Computer Architecture (HPCA), Las Vegas, NV, Jan. 1998. Google ScholarGoogle ScholarDigital LibraryDigital Library

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    • Published in

      cover image ACM SIGPLAN Notices
      ACM SIGPLAN Notices  Volume 44, Issue 4
      PPoPP '09
      April 2009
      294 pages
      ISSN:0362-1340
      EISSN:1558-1160
      DOI:10.1145/1594835
      Issue’s Table of Contents
      • cover image ACM Conferences
        PPoPP '09: Proceedings of the 14th ACM SIGPLAN symposium on Principles and practice of parallel programming
        February 2009
        322 pages
        ISBN:9781605583976
        DOI:10.1145/1504176

      Copyright © 2009 ACM

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      • Published: 14 February 2009

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