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The semantics of power and ARM multiprocessor machine code (abstract only)

Published:06 October 2009Publication History
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Abstract

We develop a rigorous semantics for Power and ARM multiprocessor programs, including their relaxed memory model and the behaviour of reasonable fragments of their instruction sets. The semantics is mechanised in the HOL proof assistant. This should provide a good basis for informal reasoning and formal verification of low-level code for these weakly consistent architectures, and, together with our x86 semantics, for the design and compilation of high-level concurrent languages.

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  1. The semantics of power and ARM multiprocessor machine code (abstract only)

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        cover image ACM SIGPLAN Notices
        ACM SIGPLAN Notices  Volume 44, Issue 5
        May 2009
        19 pages
        ISSN:0362-1340
        EISSN:1558-1160
        DOI:10.1145/1629635
        Issue’s Table of Contents

        Copyright © 2009 Authors

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        Association for Computing Machinery

        New York, NY, United States

        Publication History

        • Published: 6 October 2009

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