A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion

ABSTRACT

As VLSI technology enters the nanoscale regime, interconnect delay has become the bottleneck of the circuit timing. As one of the most powerful techniques for interconnect optimization, buffer insertion is indispensable in the physical synthesis flow. Buffering is known to be NP-complete and existing works either explore dynamic programming to compute optimal solution in the worst-case exponential time or design efficient heuristics without performance guarantee. Even if buffer insertion is one of the most studied problems in physical design, whether there is an efficient algorithm with provably good performance still remains unknown.

This work settles this open problem. In the paper, the first fully polynomial time approximation scheme for the timing driven minimum cost buffer insertion problem is designed. The new algorithm can approximate the optimal buffering solution within a factor of 1 + ε running in O(m²n²b/ε³ + n³b²/ε) time for any 0 < ε < 1, where n is the number of candidate buffer locations, m is the number of sinks in the tree, and b is the number of buffers in the buffer library. In addition to its theoretical guarantee, our experiments on 1000 industrial nets demonstrate that compared to the commonly-used dynamic programming algorithm, the new algorithm well approximates the optimal solution, with only 0.57% additional buffers and 4.6x speedup. This clearly demonstrates the practical value of the new algorithm.

References

1. P. Saxena and N. Menezes and P. Cocchini and D. A. Kirkpatrick, "Repeater scaling and its impact on CAD," TCAD, vol. 23, no. 4, pp. 451--463, 2004.
2. J. Cong, "An interconnect-centric design flow for nanometer technologies," Proceedings of the IEEE, vol. 89, no. 4, pp. 505--528, 2001.
3. Z. Li, C. Alpert, S. Hu, T. Muhmud, S. Quay, and P. Villarrubia, "Fast interconnect synthesis with layer assignment," ISPD, 2008.
4. P. J. Osler, "Placement driven synthesis case studies on two sets of two chips: hierarchical and flat," ISPD, pp. 190--197, 2004.
5. L. P. P. P. van Ginneken, "Buffer placement in distributed RC-tree networks for minimal Elmore delay," in Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 865--868, 1990.
6. J. Lillis and C.-K. Cheng and T.-T.Y. Lin, "Optimal wire sizing and buffer insertion for low power and a generalized delay model," IEEE Journal of Solid State Circuits, vol. 31, no. 3, pp. 437--447, 1996.
7. W. Shi and Z. Li, "A fast algorithm for optimal buffer insertion," TCAD, vol. 24, no. 6, pp. 879--891, 2005.
8. R. Chen and H. Zhou, "A flexible data structure for efficient buffer insertion," ICCD, 2004.
9. W. Shi and Z. Li and C. Alpert, "Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost," ASPDAC, pp. 609--614, 2004.
10. C. J. Alpert and A. Devgan and S. T. Quay, "Buffer insertion for noise and delay optimization," DAC, pp. 362--367, 1998.
11. S. Hu, C. J. Alpert, J. Hu, S. Karandikar, Z. Li, W. Shi, and C. N. Sze, "Fast algorithms for slew constrained minimum cost buffering," DAC, 2006.
12. R. Chen and H. Zhou, "Fast min-cost buffer insertion under process variations," DAC, 2007.
13. H. Zhou, D. F. Wong, I.-M. Liu, and A. Aziz, "Simultaneous routing and buffer insertion with restrictions on buffer locations," DAC, 1999.
14. T.-C. Chen, A. Chakraborty, and D. Z. Pan, "An integrated nonlinear placement framework with congestion and porosity aware buffer planning," DAC, 2008.
15. J. Cong, T. Kong, and D. Z. Pan, "Buffer block planning for interconnect-driven floorplanning," ICCAD, 1999.
16. C. J. Alpert, J. Hu, S. S. Sapatnekar and P. Villarrubia, "A practical methodology for early buffer and wire resource allocation," DAC, 2001.
17. S. Hu, Z. Li, and C. J. Alpert, "A polynomial time approximation scheme for timing constrained minimum cost layer assignment," ICCAD, 2008.
18. S. Hu, Z. Li, and C. J. Alpert, "A faster approximation scheme for timing constrained minimum cost layer assignment," ISPD, 2009.

Index Terms

• Applied computing

  • Physical sciences and engineering

    • Engineering

• Hardware

  • Electronic design automation

    • Physical design (EDA)