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A suite of microarchitectures for evaluating microcode compilers for other than for ISA interpretation

Published:01 December 1987Publication History
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Abstract

This note describes a suite of microarchitectures that has been developed for evaluating microcode compilers. These architectures are not especially appropriate for the interpretation of "normal" instruction set architectures owing primarily to the lack of efficient facilities for buffering and decoding ISA level instructions. Also, a single-level, nonpartitioned control store organization is used that may not be the optimal choice for the architectures in this family.

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  1. A suite of microarchitectures for evaluating microcode compilers for other than for ISA interpretation

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      cover image ACM SIGMICRO Newsletter
      ACM SIGMICRO Newsletter  Volume 18, Issue 4
      Dec. 1987
      35 pages
      ISSN:1050-916X
      DOI:10.1145/16360
      Issue’s Table of Contents

      Copyright © 1987 Author

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      Association for Computing Machinery

      New York, NY, United States

      Publication History

      • Published: 1 December 1987

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