Abstract
This note describes a suite of microarchitectures that has been developed for evaluating microcode compilers. These architectures are not especially appropriate for the interpretation of "normal" instruction set architectures owing primarily to the lack of efficient facilities for buffering and decoding ISA level instructions. Also, a single-level, nonpartitioned control store organization is used that may not be the optimal choice for the architectures in this family.
Index Terms
(auto-classified)A suite of microarchitectures for evaluating microcode compilers for other than for ISA interpretation
Recommendations
Exploiting parallel microprocessor microarchitectures with a compiler code generator
Special Issue: Proceedings of the 15th annual international symposium on Computer ArchitectureWith advances in VLSI technology, microprocessor designers can provide more microarchitectural parallelism to increase performance. We have identified four major forms of such parallelism: multiple microoperations issued per cycle, multiple result ...






Comments