Abstract
In an advanced System-on-Chip (SoC) for real-time applications, the arbiter of its on-chip communication subsystem needs to support multiple QoS criteria while providing a hard real-time guarantee. To fulfill both objectives, the arbitration algorithm must dynamically switch between NonReal-Time (NRT) and Real-Time (RT) modes such that use of the RT mode is minimized to best accommodate the overall QoS criteria. In this article, we define a model for this problem, and propose optimal solutions to its associated problems with static and dynamic warning-zone-length assignment. Compared with previous works, the proposed approach enables a bus arbiter to use much less RT mode in providing a Real-Time (RT) guarantee and, therefore, gives the arbiter more opportunity to employ non-RT modes to achieve better overall QoS. Experimental results show that the proposed approach reduces RT mode usage by as much as 37.1%. Moreover, that reduction in RT mode usage helps cut the execution time by 27.0% when applying our approach to an industrial DRAM controller. Another case study on an AMBA-compliant ultra-high-resolution H.264 decoder IP shows that the proposed approach reduces RT mode usage by 26.4%, which leads to an average reduction of 10.4% in decoding time. Finally, when implementing a 16 master arbiter, it costs only 6.9K and 9.5K gates of overhead using the proposed static and dynamic approach, respectively. Therefore, the proposed approach is suitable for real-time SoC applications.
Supplemental Material
Available for Download
Online appendix to an optimal warning-zone-length assignment algorithm for real-time and multiple-QoS on-chip bus arbitration on article 35.
- ARM, Inc. 1999. AMBA Specification Rev. 2.0. http://www.arm.com/products/solutions/AMBA_Spec.html.Google Scholar
- ARM, Inc. 2003. AMBA AXI Specification. http://www.arm.com/products/solutions/axi_spec.html.Google Scholar
- Bolotin, E., Cidon, I., Ginosar, R., and Kolodny, A. Qnoc: Qos architecture and design process for network on chip. J. Syst. Archit. 50, 2-3. Google Scholar
Digital Library
- Chen, C. H., Lee, G. W., Huang, J. D., and Jou, J. Y. 2006. A real-time and bandwidth guaranteed arbitration algorithm for soc bus communication. In Proceedings of the Asia South Pacific Design Automation Conference. 600--605. Google Scholar
Digital Library
- Combaz, J., Fernandez, J.-C., Lepley, T., and Sifakis, J. 2005. Fine grain qos control for multimedia application software. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition. IEEE Computer Society, 1038--1043. Google Scholar
Digital Library
- Conti, M., Caldari, M., Vece, G. B., Orcioni, S., and Turchetti, C. 2004. Performance analysis of different arbitration algorithms of the amba ahb bus. In Proceedings of the Design Automation Conference. 618--621. Google Scholar
Digital Library
- Davare1, A., Zhu, Q., Natale, M. D., Pinello, C., Kanajan, S., and Sangiovanni-Vincentelli, A. 2007. Prediction-Based flow control for network-on-chip traffic. In Proceedings of the 44th Annual Conference on Design Automation. ACM, 278--283. Google Scholar
Digital Library
- Denali, Inc. 2007. Databahn DRAM Memory Controller IP. http://www.denali.com/products/databahn_dram.html.Google Scholar
- Digital Cinama Initiatives, LLC 2008. Digital Cinema Specification Version 1.2. http://www.dcimovies.com/DCIDigitalCinemaSystemSpecv1_2.pdf.Google Scholar
- Elpeda, Inc. 2007. How to use SDRAM/DDR/DDR2 - Users Manual. http://www.elpida.com/en/products/documents.html.Google Scholar
- Franklin, G. F., Powell, J. D., and Workman, M. 1997. Digital Control for Dynamic Systems, 3rd Ed. Addison-Wisley. Google Scholar
Digital Library
- George, L., Muhlethaler, P., and Rivierre, N. 1995. Optimality and non-preemptive real-time scheduling revisited. INRIA Res. Rep. n2516.Google Scholar
- George, L., Muhlethaler, P., and Rivierre, N. 2000. A few results on non-preemptive real-time scheduling. INRIA Res. rep. n3926.Google Scholar
- Gill, C. D., Levine, D. L., and Schmidt, D. C. 2001. The design and performance of a real-time corba scheduling service. Real-Time Syst. 20, 2, 117--154. Google Scholar
Digital Library
- Goossens, K. 2004. Interconnect-Centric Design for Advanced SoC and NoC. Chapter 15. Kluwer.Google Scholar
- Goossens, K., Dielissen, J., Gangwal, O. P., Pestana, S. G., Radulescu, A., and Rijpkema, E. 2005. A design flow for application-specific networks on chip with guaranteed performance to accelerate soc design and verification. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition 2, 1182--1187. Google Scholar
Digital Library
- Howell, R. R. and Venkatrao, M. K. 1995. On non-preemptive scheduling of recurring tasks using inserted idle times. Inform. Comput. 117, 1, 50--62. Google Scholar
Digital Library
- IBM, Inc. 2001. CoreConnect Bus Architecture version 3.5. http://www-03.ibm.com/chips/products/coreconnect/.Google Scholar
- Intel, Inc. 2008. Intel 82540EM Gigabit Ethernet Controller. http://www.intel.com/design/network/products/lan/controllers/82540.htm.Google Scholar
- Jeffay, K., Stanat, D. F., and Martel, C. U. 1991. On non-preemptive scheduling of periodic and sporadic tasks. In Proceedings of the 12th IEEE Real-Time Systems Symposium. 129--139.Google Scholar
- Joint Video Team, International Telecommunication Union. 2007. H.264 : Advanced video coding for generic audiovisual services. http://www.itu.int/rec/T-REC-H.264.Google Scholar
- Jun, M., Bang, K., Lee, H.-J., Chang, N., and Chung, E.-Y. 2007. Slack-Based bus arbitration scheme for soft real-time constrained embedded systems. In Proceedings of the Asia South Pacific Design Automation Conference. 159--164. Google Scholar
Digital Library
- Kim, S., Lee, J., and Lee, J. 2006. Runtime feasibility check for non-preemptive real-time periodic tasks. Inform. Process. Lett. 97, 3, 83--87. Google Scholar
Digital Library
- Lahiri, K., Dey, S., and Raghunathan, A. 2001. Evaluation of the traffic-performance characteristics of system-on-chip communication architectures. In Proceedings of the International Conference on VLSI Design, 29. Google Scholar
Digital Library
- Lahiri, K., Raghunathan, A., and Lakshminarayana, G. 2006. The lotterybus on-chip communication architecture. IEEE Trans. VLSI Syst. 14, 6, 596--608. Google Scholar
Digital Library
- Lee, A. S. C. 2007. Comprehensive system-level analysis and optimization with milti-QoS considerations on a H.264 video decoder SoC. M.S. thesis, National Tsing Hua University, Hsinchu, Taiwan.Google Scholar
- Lee, K. B., Lin, T. C., and Jen, C. W. 2005. An efficient quality-aware memory controller for multimedia platform soc. IEEE Trans. Circ. Syst. Video Technol. 15, 620--633. Google Scholar
Digital Library
- Lin, B.-C., Lee, G.-W., Huang, J.-D., and Jou, J.-Y. 2007. A precise bandwidth control arbitration algorithm for hard real-time soc buses. In Proceedings of the Asia and South Pacific Design Automation Conference, 165--170. Google Scholar
Digital Library
- Liu, C. L. and Layland, J. W. 1973. Scheduling algorithms for multiprogramming in a hard-healtime environment. J. Assoc. Comput. Mach. 20, 1, 46--61. Google Scholar
Digital Library
- Lu, C., Abdelzaher, T. F., Stankovic, J. A., and Son, S. H. 2001. A feedback control approach for guaranteeing relative delays in web servers. In Proceedings of the 7th Real-Time Technology and Applications Symposium (RTAS '01). IEEE Computer Society, 51. Google Scholar
Digital Library
- Lu, R. and Koh, C.-K. 2005. Improving the scalability of samba bus architecture. In Proceedings of the Asia and South Pacific Design Automation Conference. 1164--1167. Google Scholar
Digital Library
- Meyerowitz, T., Pinello, C., and Sangiovanni-Vincentelli, A. 2003. A tool for describing and evaluating hierarchical real-time bus scheduling policies. In Proceedings of the Design Automation Conference. 312. Google Scholar
Digital Library
- Motion Picture Experts Group. 2007. Coding of moving pictures and associated audio for digital storage media at up to about 1.5 Mbit/s -- Part 3: Audio. http://www.chiariglione.org/mpeg/standards/mpeg-1/mpeg-1.htm.Google Scholar
- Ogras, U. Y. and Marculescu, R. 2006. Prediction-Based flow control for network-on-chip traffic. In Proceedings of the 43rd Annual Conference on Design Automation. ACM, 839--844. Google Scholar
Digital Library
- OPENCORES. 2002. WISHBONE SoC interconnection architecture for portable IP cores Rev.B3. http://www.opencores.org/projects.cgi/web/wishbone/wbspec_b3.pdf.Google Scholar
- OPENCORES. 2007. OCP 2.2 specification. http://www.ocpip.org/membership/information/wheel/specification/.Google Scholar
- Peng, H. K., Lee, C. H., Chen, J. W., Lo, T. J., Chang, Y. H., Hsu, S. T., Lin, Y. C., Chao, P., Hung, W. C., and Jan, K. Y. 2007a. A highly integrated 8mw h.264/avc main profile real-time cif video decoder on a 16mhz soc platform. In Proceedings of the Asia South Pacific Design Automation Conference. 112--113.Google Scholar
- Peng, H. K., Lee, C. H., Hsu, S. T., and Hung, W. C. 2007b. A 4Kx2K real-time H.264 decoder IP. Rep. of the 2007 National Silicon Intelectual Property Contest, http://140.114.75.173/QFHD/.Google Scholar
- Pestana, S. G., Rijpkema, E., R?dulescu, A., Goossens, K., and Gangwal, O. P. 2004. Cost-Performance trade-offs in networks on chip: A simulation-based approach. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition 2. 20764. Google Scholar
Digital Library
- Poletti, F., Bertozzi, D., Benini, L., and Bogliolo, A. 2003. Performance analysis of arbitration policies for soc communication architectures. Des. Autom. Embedd. Syst. 8, 2-3, 189--210.Google Scholar
Digital Library
- Puterman, M. L. 1994. Marov Decision Processes: Discrete Stochastic Dynamic Programming. Wiley-Interscience, New York. Google Scholar
Digital Library
- Richardson, T. D., Nicopoulos, C., Park, D., Narayanan, V., Xie, Y., Das, C., and Degalahal, V. 2006. A hybrid soc interconnect with dynamic tdma-based transaction-less buses and on-chip networks. In Proceedings of the International Conference on VLSI Design. 657--664. Google Scholar
Digital Library
- Sha, L., Abdelzaher, K., Arzen, K., Cervin, A., Baker, T., Burns, A., Buttazzo, G., Caccamo, M., Lehoczky, J., and Mok, A. K. 2004. Real time theory: A historical perspective. Realtime Syst. 28, 101--155. Google Scholar
Digital Library
- Sha, L., Rajkumar, R., Lehoczky, J., and Ramamritham, K. 1989. Mode change protocols for priority-driven preemptive scheduling. Tech. rep., Amherst, MA. Google Scholar
Digital Library
- STMicroelectronics. 2006. STBus interconnect. http://www.st.com/stonline/products/technologies/soc/stbus.htm.Google Scholar
- Sutton, R. S. and Barto, A. G. 1998. Reinforcement Learning: An Introduction. MIT Press, Cambridge, MA. Google Scholar
Digital Library
- Swaminathan, V. and Chakrabarty, K. 2005. Pruning-Based, energy-optimal, deterministic i/o device scheduling for hard real-time systems. ACM Trans. Embed. Comput. Syst. 4, 1, 141--167. Google Scholar
Digital Library
- Synopsis. 2005. PrimePower Manual Version 2005.09. Synopsis.Google Scholar
- Takizawa, T. and Hirasawa, M. 2001. An efficient memory arbitration algorithm for a single chip mpeg2 av decoder. IEEE Trans. Consumer Electron. 47, 3, 660--665. Google Scholar
Digital Library
- Wüst, C. C., Steffens, L., Verhaegh, W. F., Bril, R. J., and Hentschel, C. 2005. Qos control strategies for high-quality video processing. Real-Time Syst. 30, 1-2, 7--29. Google Scholar
Digital Library
Index Terms
An optimal warning-zone-length assignment algorithm for real-time and multiple-QoS on-chip bus arbitration
Recommendations
A survey of research and practices of Network-on-chip
The scaling of microchip technologies has enabled large scale systems-on-chip (SoC). Network-on-chip (NoC) research addresses global communication in SoC, involving (i) a move from computation-centric to communication-centric design and (ii) the ...
Latency-Aware Bus Arbitration for Real-Time Embedded Systems
We present a latency-aware bus arbitration scheme for real-time embedded systems. Only a few works have addressed the quality of service (QoS) issue for traditional busses or interconnection network. They mostly aimed at minimizing the latencies of ...
Performance Comparison of AMBA Bus-Based System-On-Chip Communication Protocol
CSNT '11: Proceedings of the 2011 International Conference on Communication Systems and Network TechnologiesModern computer system rely more and more on -- chip communication protocol to exchange data. System-on-chip (SoC) designs use bus protocols for high performance data transfer among the Intellectual Propert (IP) cores. These protocols incorporate ...






Comments