ABSTRACT
Concurrent Action-Oriented Specifications (CAOS) model the be- havior of a synchronous hardware circuit as asynchronous guarded actions at an abstraction level higher than the Register Transfer Level (RTL). Previous approaches always considered the compilation of CAOS, which includes a transformation of the under-lying model of computation and the scheduling of guarded actions per clock cycle, as a tightly integrated step. In this paper, we present a new compilation procedure, which separates these two tasks and translates CAOS models to synchronous guarded actions with an explicit interface to a scheduler. This separation of con- cerns has many advantages, including better analyses and integration of custom schedulers. Our method also generates assertions that each scheduler must obey that can be fulfilled by algorithms for scheduler synthesis like those developed in supervisory control. We present our translation procedure in detail and illustrate it by various examples. We also show that our method simplifies for- mal verification of hardware synthesized from CAOS specifications over previously known formal verification approaches.
- A. Benveniste, P. Caspi, S. Edwards, N. Halbwachs, P. Le Guernic, and R. de Simone. The synchronous languages twelve years later. Proceedings of the IEEE, 91(1):64--83, 2003.Google Scholar
Cross Ref
- G. Berry. A hardware implementation of pure Esterel. In Workshop on Formal Methods in VLSI Design, Miami, Florida, 1991.Google Scholar
- G. Berry. Synchronous languages for hardware and software reactive systems. In C. Delgado Kloos and E. Cerny, editors, Conference on Computer Hardware Description Languages and Their Applications (CHDL), Toledo, Spain, 1997. Chapman & Hall. Google Scholar
Digital Library
- J. Brandt and K. Schneider. Separate compilation of synchronous programs. In Software and Compilers for Embedded Systems (SCOPES), volume 320 of ACM International Conference Proceeding Series, pages 1--10, Nice, France, 2009. ACM. Google Scholar
- K. Chandy and J. Misra. Parallel Program Design. Addison Wesley, Austin, Texas, May 1989. Google Scholar
Digital Library
- N. Dave, Arvind, and M. Pellauer. Scheduling as rule composition. In International Conference on Formal Methods and Models for Codesign (MEMOCODE), pages 51--60, Nice, France, 2007. IEEE Computer Society. Google Scholar
Digital Library
- E. Dijkstra. Guarded commands, nondeterminacy and formal derivation of programs. Communications of the ACM, 18(8):453--457, 1975. Google Scholar
Digital Library
- D. Dill. The Murphi verification system. In R. Alur and T. Henzinger, editors, Computer Aided Verification (CAV), volume 1102 of LNCS, pages 390--393, New Brunswick, NJ, USA, 1996. Springer. Google Scholar
Digital Library
- N. Halbwachs.Synchronous programming of reactive systems. Kluwer, 1993. Google Scholar
Digital Library
- J. Hoe and Arvind. Operation-centric hardware description and synthesis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 23(9):1277--1288, September 2004. Google Scholar
Digital Library
- G. Holzmann. The Spin Model Checker: Primer and Reference Manual. Addison-Wesley, 2004. Google Scholar
Digital Library
- H. Järvinen and R. Kurki-Suonio. The DisCo language and temporal logic of actions. Technical Report 11, Tampere University of Technology, Software Systems Laboratory, 1990.Google Scholar
- L. Lamport. The temporal logic of actions. Technical Report 79, Digital Equipment Cooperation, 1991.Google Scholar
- P. Ramadge and W. Wonham. Supervisory control of a class of discrete event processes. SIAM Journal of Control and Optimization, 25(1): 206--230, 1987. Google Scholar
Digital Library
- F. Rocheteau and N. Halbwachs. Pollux, a Lustre-based hardware design environment. In P. Quinton and Y. Robert, editors, Conference on Algorithms and Parallel VLSI Architectures II, Chateau de Bonas, 1991. Google Scholar
Digital Library
- D. Rosenband and Arvind. Modular scheduling of guarded atomic actions. In Design Automation Conference (DAC), pages 55--60, San Diego, CA, USA, 2004. ACM. Google Scholar
Digital Library
- K. Schneider. Embedding imperative synchronous languages in interactive theorem provers. In Conference on Application of Concurrency to System Design (ACSD), pages 143--154, Newcastle upon Tyne, UK, 2001. IEEE Computer Society. Google Scholar
Digital Library
- K. Schneider. Proving the equivalence of microstep and macrostep semantics. In V. Carreño, C. Muñoz, and S. Tahar, editors, Theorem Proving in Higher Order Logics (TPHOL), volume 2410 of LNCS, pages 314--331, Hampton, VA, USA, 2002. Springer. Google Scholar
Digital Library
- K. Schneider. The synchronous programming language Quartz. Internal Report 375, Department of Computer Science, University of Kaiserslautern, Kaiserslautern, Germany, 2009.Google Scholar
- K. Schneider and J. Brandt. Performing causality analysis by bounded model checking. In Conference on Application of Concurrency to System Design (ACSD), pages 78--87, Xi'an, China, 2008. IEEE Computer Society.Google Scholar
Cross Ref
- K. Schneider, J. Brandt, and T. Schuele. Causality analysis of synchronous programs with delayed actions. In Compilers, Architecture, and Synthesis for Embedded Systems (CASES), pages 179--189, Washington, DC, USA, 2004. ACM. Google Scholar
Digital Library
- K. Schneider, J. Brandt, T. Schuele, and T. Tuerk. Maximal causality analysis. In J. Desel and Y. Watanabe, editors, Application of Concurrency to System Design (ACSD), pages 106--115, St. Malo, France, 2005. IEEE Computer Society. Google Scholar
Digital Library
- K. Schneider, J. Brandt, and T. Schuele. A verified compiler for synchronous programs with local declarations. Electronic Notes in Theoretical Computer Science (ENTCS), 153(4):71--97, 2006. Google Scholar
Digital Library
- T. Shiple. Formal Analysis of Synchronous Circuits. PhD thesis, University of California at Berkeley, Berkeley, CA, USA, 1996. Google Scholar
Digital Library
- G. Singh and S. Shukla. Algorithms for low power hardware synthesis from concurrent action oriented specifications CAOS. International Journal of Embedded Systems (IJES), 3(1/2):83--92, 2007.Google Scholar
- G. Singh and S. Shukla. Verifying compiler based refinement of Bluespec specifications using the SPIN model checker. In K. Havelund, R. Majumdar, and J. Palsberg, editors, Model Checking Software (SPIN), volume 5156 of LNCS, pages 250--269, Los Angeles, CA, USA, 2008. Springer. Google Scholar
Digital Library
- R. Ziller and K. Schneider. Combining supervisor synthesis and model checking. Transactions on Embedded Computing Systems (TECS), 4 (2):331--362, May 2005. Google Scholar
Digital Library
Index Terms
Translating concurrent action oriented specifications to synchronous guarded actions
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