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Translating concurrent action oriented specifications to synchronous guarded actions

Published:13 April 2010Publication History

ABSTRACT

Concurrent Action-Oriented Specifications (CAOS) model the be- havior of a synchronous hardware circuit as asynchronous guarded actions at an abstraction level higher than the Register Transfer Level (RTL). Previous approaches always considered the compilation of CAOS, which includes a transformation of the under-lying model of computation and the scheduling of guarded actions per clock cycle, as a tightly integrated step. In this paper, we present a new compilation procedure, which separates these two tasks and translates CAOS models to synchronous guarded actions with an explicit interface to a scheduler. This separation of con- cerns has many advantages, including better analyses and integration of custom schedulers. Our method also generates assertions that each scheduler must obey that can be fulfilled by algorithms for scheduler synthesis like those developed in supervisory control. We present our translation procedure in detail and illustrate it by various examples. We also show that our method simplifies for- mal verification of hardware synthesized from CAOS specifications over previously known formal verification approaches.

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      • Published in

        cover image ACM Conferences
        LCTES '10: Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems
        April 2010
        184 pages
        ISBN:9781605589534
        DOI:10.1145/1755888
        • cover image ACM SIGPLAN Notices
          ACM SIGPLAN Notices  Volume 45, Issue 4
          LCTES '10
          April 2010
          170 pages
          ISSN:0362-1340
          EISSN:1558-1160
          DOI:10.1145/1755951
          Issue’s Table of Contents

        Copyright © 2010 ACM

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        Association for Computing Machinery

        New York, NY, United States

        Publication History

        • Published: 13 April 2010

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