skip to main content
10.1145/1806651.1806660acmconferencesArticle/Chapter ViewAbstractPublication PagesismmConference Proceedingsconference-collections
keynote

Memory, an elusive abstraction

Published:05 June 2010Publication History

ABSTRACT

Multiprocessors are now ubiquitous. They provide an abstraction of shared memory, accessible by concurrently executing threads, which supports a wide range of software. However, exactly what this key abstraction is -- what the hardware designers implement, and what programmers can depend on -- is surprisingly elusive. In 1979, when articulating the notion of sequential consistency (SC), Lamport wrote "For some applications, achieving sequential consistency may not be worth the price of slowing down the processors." [7], and indeed most major multiprocessor families, including Alpha, ARM, Itanium, Power, Sparc, and x86, do not provide the abstraction of SC memory. Internally, they incorporate a range of sophisticated optimisations which have various programmer-visible effects. For some (such as Sparc) these effects are captured in a well-defined relaxed memory model, making it possible (if challenging) to reason with confidence about the behaviour of concurrent programs. For others, however, it has been very unclear what a reasonable model is, despite extensive research over the last three decades. In this talk, I will reflect on the experience of my colleagues and I in trying to establish usable models for x86 multiprocessors, where it appears that our x86-TSO model suffices for common-case code [1-4], and for Power and ARM multiprocessors, where we have models that capture some but not all aspects of their behaviour [5,6]. The underlying causes of these difficulties are complex, including:

  • The programmer-observable relaxed-memory behaviour of a multiprocessor is a whole-system property that arises from the interaction between many complex aspects of the processor implementation: speculative execution, store buffering, cache protocol, and so forth.

  • Programs are executed (and tested) on specific multiprocessor implementations, but processor vendors attempt to document loose specifications to cover a range of possible (past and future) implementations

  • Multiprocessor implementation details are typically confidential and may change radically from one implementation to another

  • Vendor specifications suffer from the tension between the need for loose specification, to preserve freedom for such changes, and the need for tight specification, to give strong properties to properties

  • All too often, loose specification has been achieved by vague specification, using informal prose. When it comes to subtle concurrent properties this is almost inevitably ambiguous; it also makes it impossible (even in principle) to test conformance between a processor implementation and such a specification, let alone to verify such a correspondence or to reason about concurrent programs.

References

  1. S. Sarkar, P. Sewell, F. Zappa Nardelli, S. Owens, T. Ridge, T. Braibant, M. Myreen, and J. Alglave. The semantics of x86-CC multiprocessor machine code. In Proc. POPL 2009, January 2009. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. Scott Owens, Susmit Sarkar, and Peter Sewell. A better x86 memory model: x86-TSO. In Proc. TPHOLs, LNCS 5674, pages 391--407, 2009. Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. Scott Owens. Reasoning about the implementation of concurrency abstractions on x86-TSO. In Proc. ECOOP, 2010. To appear.Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. Peter Sewell, Susmit Sarkar, Scott Owens, Francesco Zappa Nardelli, and Magnus Myreen. x86-TSO: A rigorous and usable programmer's model for x86 multiprocessors. Communications of the ACM, 2010. To appear. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. J. Alglave, A. Fox, S. Ishtiaq, M. Myreen, S. Sarkar, P. Sewell, and F. Zappa Nardelli. The semantics of Power and ARM multiprocessor machine code. In Proc. DAMP 2009, January 2009. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. Jade Alglave, Luc Maranget, Susmit Sarkar, and Peter Sewell. Fences in weak memory models. In Proceedings of CAV, 2010. To appear.Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. L. Lamport. How to make a multiprocessor computer that correctly executes multiprocess programs. IEEE Trans. Comput., C-28(9):690--691, 1979. Google ScholarGoogle ScholarDigital LibraryDigital Library

Index Terms

  1. Memory, an elusive abstraction

            Recommendations

            Comments

            Login options

            Check if you have access through your login credentials or your institution to get full access on this article.

            Sign in
            • Published in

              cover image ACM Conferences
              ISMM '10: Proceedings of the 2010 international symposium on Memory management
              June 2010
              140 pages
              ISBN:9781450300544
              DOI:10.1145/1806651
              • General Chair:
              • Jan Vitek,
              • Program Chair:
              • Doug Lea
              • cover image ACM SIGPLAN Notices
                ACM SIGPLAN Notices  Volume 45, Issue 8
                ISMM '10
                August 2010
                129 pages
                ISSN:0362-1340
                EISSN:1558-1160
                DOI:10.1145/1837855
                Issue’s Table of Contents

              Copyright © 2010 Copyright is held by the author/owner(s)

              Publisher

              Association for Computing Machinery

              New York, NY, United States

              Publication History

              • Published: 5 June 2010

              Permissions

              Request permissions about this article.

              Request Permissions

              Check for updates

              Qualifiers

              • keynote

              Acceptance Rates

              Overall Acceptance Rate72of156submissions,46%

            PDF Format

            View or Download as a PDF file.

            PDF

            eReader

            View online with eReader.

            eReader
            About Cookies On This Site

            We use cookies to ensure that we give you the best experience on our website.

            Learn more

            Got it!