ABSTRACT
Caches were designed to amortize the cost of memory accesses by moving copies of frequently accessed data closer to the processor. Over the years the increasing gap between processor speed and memory access latency has made the cache a bottleneck for program performance. Enhancing cache performance has been instrumental in speeding up programs. For this reason several hardware and software techniques have been proposed by researchers to optimize the cache for minimizing the number of misses. Among these are compile-time data placement techniques in memory which improve cache performance. For the purpose of this work, we concern ourselves with the problem of laying out data in memory given the sequence of accesses on a finite set of data objects such that cache-misses are minimized. The problem has been shown to be hard to solve optimally even if the sequence of data accesses is known at compile time. In this paper we show that given a direct-mapped cache, its size, and the data access sequence, it is possible to identify the instances where there are no conflict misses. We describe an algorithm that can assign the data to cache for minimal number of misses if there exists a way in which conflict misses can be avoided altogether. We also describe the implementation of a heuristic for assigning data to cache for instances where the size of the cache forces conflict misses. Experiments show that our technique results in a 30% reduction in the number of cache misses compared to the original assignment.
- A. Aggarwal. Software Caching vs. Prefetching. In ISMM '02: Proceedings of the 3rd International Symposium on Memory Management, pages 157--162, 2002. Google Scholar
Digital Library
- A. H. Badawy, A. Aggarwal, D. Yeung, and C. Tseng. Evaluating the Impact of Memory System Performance on Software Prefetching and Locality Optimizations. In ICS '01: Proceedings of the 15th International Conference on Supercomputing, pages 486--500, 2001. Google Scholar
Digital Library
- R. E. Bixby, K. Kennedy, and U. Kremer. Automatic Data Layout Using 0-1 Integer Programming. In PACT '94: Proceedings of the IFIP WG10.3Working Conference on Parallel Architectures and Compilation Techniques, pages 111--122, 1994. Google Scholar
Digital Library
- B. Calder, C. Krintz, S. John, and T. Austin. Cache-Conscious Data Placement. In ASPLOS VIII: Proceedings of the 8th International Conference on Architectural Support for Programming Languages and Operating Systems, pages 139--149, 1998. Google Scholar
Digital Library
- D. Callahan, K. Kennedy, and A. Porterfield. Software Prefetching. In ASPLOS IV: Proceedings of the Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, pages 40--52, April 08-11, 1991. Google Scholar
Digital Library
- T. M. Chilimbi. Efficient Representations and Abstractions for Quantifying and Exploiting Data Reference Locality. In PLDI '01: Proceedings of the ACM SIGPLAN 2001 Conference on Programming Language Design and Implementation, pages 191--202, 2001. Google Scholar
Digital Library
- T. M. Chilimbi, B. Davidson, and J. R. Larus. Cache-Conscious Structure Definition. In PLDI '99: Proceedings of the ACM SIGPLAN Conference on Programming Languages Design and Implementation, 1--12, 1999. Google Scholar
Digital Library
- T. M. Chilimbi, M. D. Hill, and J. R. Larus. Cache-Conscious Structure Layout. In PLDI '99: Proceedings of the ACM SIGPLAN Conference on Programming Languages Design and Implementation, 1--12, 1999. Google Scholar
Digital Library
- T. M. Chilimbi, and M. Hirzel. Dynamic Hot Data Stream Prefetching for General-Purpose Programs. In PLDI '02: Proceedings of the ACM SIGPLAN 2002 Conference on Programming language design and implementation, June 17-19, 2002. Google Scholar
Digital Library
- T. M. Chilimbi, and J. R. Larus. Using Generational Garbage Collection to Implement Cache-Conscious Data Placement. In ISMM '98: Proceedings of the 1st International Symposium on Memory Management, 37--48, 1998. Google Scholar
Digital Library
- S. Curial, P. Zhao, J. N. Amaral, Y. Gao, S. Cui, R. Silvera, and R. Archambault. Memory Pooling Assisted Data Splitting (MPADS). Proceedings of the 7th International Symposium on Memory Management, June 07-08, pages 101--110, 2008, Tucson, AZ, USA Google Scholar
Digital Library
- C. Ding, and K. Kennedy. Improving Cache Performance in Dynamic Applications through Data and Computation Reorganization at Run Time. In PLDI '99: Proceedings of the ACM SIGPLAN 1999 Conference on Programming Language Design and Implementation, pages 229--241, May 01-04, 1999. Google Scholar
Digital Library
- C. Ding, and Y. Zhong. Predicting Whole-Program Locality through Reuse Distance Analysis. In PLDI '03: Proceedings of the ACM SIGPLAN 2003 Conference on Programming Language Design and Implementation, pages 245--257, 2003. Google Scholar
Digital Library
- M. C. Golumbic. Algorithmic Graph Theory and Perfect Graphs (Annals of Discrete Mathematics, Vol 57). North-Holland Publishing Co., Amsterdam, The Netherlands, The Netherlands, 2004 Google Scholar
Digital Library
- X. Gu, I. Christopher, T. Bai, C. Zhang, and C. Ding. A Component Model of Spatial Locality. Proceedings of the 2009 International Symposium on Memory Management, June 19-20, 2009, Dublin, Ireland Google Scholar
Digital Library
- J. L. Hennessy, D. A. Patterson, and A. C. Arpaci-Dusseau. Computer Architecture: A Quantitative Approach. Fourth Edition, 2007. Morgan Kaufman Publishers. Google Scholar
Digital Library
- G. Jin, J. Mellor-Crummey, and R. Fowler. Increasing Temporal Locality with Skewing and Recursive Blocking. Proceedings of the 2001 ACM/IEEE conference on Supercomputing, pages 43--43, 2001. Google Scholar
Digital Library
- A. Jula, and L. Rauchwerger. Two Memory Allocators that use Hints to Improve Locality. In ISMM '09: Proceedings of the 2009 International Symposium on Memory Management, June 19-20, 2009. Google Scholar
Digital Library
- C. Lattner, and V. Adve. Automatic Pool Allocation: Improving Performance by Controlling Data Structure Layout in the Heap. In PLDI '05: Proceedings of the 2005 ACM SIGPLAN Conference on Programming Language Design and Implementation, pages 129--142, 2005. Google Scholar
Digital Library
- E. Petrank, and D. Rawitz. The Hardness of Cache Conscious Data Placement. In POPL '02: Proceedings of the 29th ACM SIGPLANSIGACT symposium on Principles of Programming Languages, pages 101--112, 2002. Google Scholar
Digital Library
- E. Petrank, and D. Rawitz. The Hardness of Cache Conscious Data Placement. Nordic Journal of Computing, vol 12(3), pages 275--307, 2005. Google Scholar
Digital Library
- G. B. Prokopski, and C. Verbrugge. Analyzing the Performance of Code-Copying Virtual Machines. In OOPSLA '08: Proceedings of the 23rd ACM SIGPLAN Conference on Object-Oriented Programming Systems Languages and Applications, pages 403--422, 2008. Google Scholar
Digital Library
- X. Shen, J. Shaw, B. Meeker, and C. Ding. Locality Approximation Using Time. In POPL '07: Proceedings of the 34th annual ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, pages 55--61, 2007. Google Scholar
Digital Library
- K. O.Thabit. Cache Management by the Compiler. Ph.D. thesis, Rice University, 1982. Google Scholar
Digital Library
- M. E. Wolf, D. E. Maydan, and D. Chen. Combining Loop Transformations Considering Caches and Scheduling. In the International Journal of Parallel Programming, vol 26(4), pages 479--503 1998. Google Scholar
Digital Library
- C. Zhang, C. Ding, M. Ogihara, Y. Zhong, and Y. Wu. A Hierarchical Model of Data Locality. In POPL '06: Conference of the 33rd ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, pages 16--29, 2006. Google Scholar
Digital Library
- Y. Zhong, amd W. Chang. Sampling-based Program Locality Approximation. Proceedings of the 7th International Symposium on Memory Management, June 07-08, 2008, Tucson, AZ, USA Google Scholar
Digital Library
- Y. Zhong, X. Shen, and C. Ding. Program Locality Analysis using Reuse Distance. ACM Transactions on Programming Languages and Systems (TOPLAS), v.31 n.6, p.1--39, August 2009 Google Scholar
Digital Library
Index Terms
A graph theoretic approach to cache-conscious placement of data for direct mapped caches
Recommendations
A graph theoretic approach to cache-conscious placement of data for direct mapped caches
ISMM '10Caches were designed to amortize the cost of memory accesses by moving copies of frequently accessed data closer to the processor. Over the years the increasing gap between processor speed and memory access latency has made the cache a bottleneck for ...
The hardness of cache conscious data placement
POPL '02: Proceedings of the 29th ACM SIGPLAN-SIGACT symposium on Principles of programming languagesThe growing gap between the speed of memory access and cache access has made cache misses an influential factor in program efficiency. Much effort has been spent recently on reducing the number of cache misses during program run. This effort includes ...
Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers
Special Issue: Proceedings of the 17th annual international symposium on Computer ArchitectureProjections of computer technology forecast processors with peak performance of 1,000 MIPS in the relatively near future. These processors could easily lose half or more of their performance in the memory hierarchy if the hierarchy design is based on ...







Comments